; generated by Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]
; commandline ArmCC [--list --debug -c --asm --interleave -o.\obj\timer.o --asm_dir=.\list\ --list_dir=.\list\ --depend=.\obj\timer.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931 -I.\FWlib\inc -I.\user -I.\CM3 -I.\dmp -I.\RTE\_STM32-FD -If:\Users\Administrator\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -If:\Users\Administrator\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=530 -D_RTE_ -DSTM32F10X_MD -D_RTE_ -DUSE_STDPERIPH_DRIVER -DSTM32F10X_MD --omf_browse=.\obj\timer.crf user\timer.c]
                          THUMB

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  timer2_ini PROC
;;;11     ****************************************************************************/ 
;;;12     void timer2_ini(void){
000000  b51f              PUSH     {r0-r4,lr}
;;;13        NVIC_InitTypeDef  NVIC_InitStructure;
;;;14        //ʱΪ˲5msĸƵ 
;;;15        TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
;;;16        //TIM2ʱ
;;;17        RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2,ENABLE);
000002  2101              MOVS     r1,#1
000004  4608              MOV      r0,r1
000006  f7fffffe          BL       RCC_APB1PeriphClockCmd
;;;18        //½TimerΪȱʡֵ
;;;19        TIM_DeInit(TIM2);
00000a  f04f4080          MOV      r0,#0x40000000
00000e  f7fffffe          BL       TIM_DeInit
;;;20        //ڲʱӸTIM2ṩʱԴ
;;;21        TIM_InternalClockConfig(TIM2);
000012  f04f4080          MOV      r0,#0x40000000
000016  f7fffffe          BL       TIM_InternalClockConfig
;;;22        TIM_TimeBaseStructure.TIM_Prescaler =7199;
00001a  f641401f          MOV      r0,#0x1c1f
00001e  f8ad0000          STRH     r0,[sp,#0]
;;;23        //ʱӷָ
;;;24        TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1;
000022  2000              MOVS     r0,#0
000024  f8ad0006          STRH     r0,[sp,#6]
;;;25        //üģʽΪϼģʽ
;;;26        TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
000028  f8ad0002          STRH     r0,[sp,#2]
;;;27        TIM_TimeBaseStructure.TIM_Period = 49;//5ms  
00002c  2031              MOVS     r0,#0x31
00002e  f8ad0004          STRH     r0,[sp,#4]
;;;28        //ӦõTIM2
;;;29        TIM_TimeBaseInit(TIM2,&TIM_TimeBaseStructure);
000032  4669              MOV      r1,sp
000034  0780              LSLS     r0,r0,#30
000036  f7fffffe          BL       TIM_TimeBaseInit
;;;30        //жϱ־
;;;31        TIM_ClearFlag(TIM2, TIM_FLAG_Update);
00003a  2101              MOVS     r1,#1
00003c  0788              LSLS     r0,r1,#30
00003e  f7fffffe          BL       TIM_ClearFlag
;;;32     	 
;;;33     	 
;;;34     	 NVIC_InitStructure.NVIC_IRQChannel=TIM2_IRQn;                   
000042  201c              MOVS     r0,#0x1c
000044  f88d000c          STRB     r0,[sp,#0xc]
;;;35     	 NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE;                   
000048  2001              MOVS     r0,#1
00004a  f88d000f          STRB     r0,[sp,#0xf]
;;;36     	 NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=0x00;      
00004e  2000              MOVS     r0,#0
000050  f88d000d          STRB     r0,[sp,#0xd]
;;;37     	 NVIC_InitStructure.NVIC_IRQChannelSubPriority =0x03;            
000054  2003              MOVS     r0,#3
000056  f88d000e          STRB     r0,[sp,#0xe]
;;;38     	 NVIC_Init(&NVIC_InitStructure); 
00005a  a803              ADD      r0,sp,#0xc
00005c  f7fffffe          BL       NVIC_Init
;;;39     	
;;;40        //ֹARRԤװػ
;;;41       // TIM_ARRPreloadConfig(TIM2, DISABLE);
;;;42        //TIM3ж
;;;43     	 
;;;44        TIM_ITConfig(TIM2,TIM_IT_Update,ENABLE);
000060  2201              MOVS     r2,#1
000062  4611              MOV      r1,r2
000064  0790              LSLS     r0,r2,#30
000066  f7fffffe          BL       TIM_ITConfig
;;;45     	 Moto_tim2_ct=0;
00006a  2000              MOVS     r0,#0
00006c  4903              LDR      r1,|L1.124|
00006e  6008              STR      r0,[r1,#0]  ; Moto_tim2_ct
;;;46        TIM_Cmd(TIM2,ENABLE);   	   
000070  2101              MOVS     r1,#1
000072  0788              LSLS     r0,r1,#30
000074  f7fffffe          BL       TIM_Cmd
;;;47     }
000078  bd1f              POP      {r0-r4,pc}
;;;48     
                          ENDP

00007a  0000              DCW      0x0000
                  |L1.124|
                          DCD      Moto_tim2_ct
