; generated by ARM C/C++ Compiler with , RVCT4.0 [Build 524] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\obj\stm32f10x_tim.o --depend=.\obj\stm32f10x_tim.d --device=DARMSTM --apcs=interwork -O0 -I.\FWlib\inc -I.\user -I.\CM3 -Id:\Keil\ARM\INC\ST\STM32F10x -D__MICROLIB -DUSE_STDPERIPH_DRIVER -DSTM32F10X_MD --omf_browse=.\obj\stm32f10x_tim.crf FWlib\SRC\stm32f10x_tim.c]
                          THUMB

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  TIM_DeInit PROC
;;;121      */
;;;122    void TIM_DeInit(TIM_TypeDef* TIMx)
000000  b510              PUSH     {r4,lr}
;;;123    {
000002  4604              MOV      r4,r0
;;;124      /* Check the parameters */
;;;125      assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
;;;126     
;;;127      if (TIMx == TIM1)
000004  48ff              LDR      r0,|L1.1028|
000006  4284              CMP      r4,r0
000008  d108              BNE      |L1.28|
;;;128      {
;;;129        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
00000a  2101              MOVS     r1,#1
00000c  14c0              ASRS     r0,r0,#19
00000e  f7fffffe          BL       RCC_APB2PeriphResetCmd
;;;130        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);  
000012  2100              MOVS     r1,#0
000014  14e0              ASRS     r0,r4,#19
000016  f7fffffe          BL       RCC_APB2PeriphResetCmd
00001a  e0c4              B        |L1.422|
                  |L1.28|
;;;131      }     
;;;132      else if (TIMx == TIM2)
00001c  f1b44f80          CMP      r4,#0x40000000
000020  d108              BNE      |L1.52|
;;;133      {
;;;134        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
000022  2101              MOVS     r1,#1
000024  4608              MOV      r0,r1
000026  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;135        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
00002a  2100              MOVS     r1,#0
00002c  2001              MOVS     r0,#1
00002e  f7fffffe          BL       RCC_APB1PeriphResetCmd
000032  e0b8              B        |L1.422|
                  |L1.52|
;;;136      }
;;;137      else if (TIMx == TIM3)
000034  48f4              LDR      r0,|L1.1032|
000036  4284              CMP      r4,r0
000038  d108              BNE      |L1.76|
;;;138      {
;;;139        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
00003a  2101              MOVS     r1,#1
00003c  2002              MOVS     r0,#2
00003e  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;140        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
000042  2100              MOVS     r1,#0
000044  2002              MOVS     r0,#2
000046  f7fffffe          BL       RCC_APB1PeriphResetCmd
00004a  e0ac              B        |L1.422|
                  |L1.76|
;;;141      }
;;;142      else if (TIMx == TIM4)
00004c  48ef              LDR      r0,|L1.1036|
00004e  4284              CMP      r4,r0
000050  d108              BNE      |L1.100|
;;;143      {
;;;144        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
000052  2101              MOVS     r1,#1
000054  2004              MOVS     r0,#4
000056  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;145        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
00005a  2100              MOVS     r1,#0
00005c  2004              MOVS     r0,#4
00005e  f7fffffe          BL       RCC_APB1PeriphResetCmd
000062  e0a0              B        |L1.422|
                  |L1.100|
;;;146      } 
;;;147      else if (TIMx == TIM5)
000064  48ea              LDR      r0,|L1.1040|
000066  4284              CMP      r4,r0
000068  d108              BNE      |L1.124|
;;;148      {
;;;149        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
00006a  2101              MOVS     r1,#1
00006c  2008              MOVS     r0,#8
00006e  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;150        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
000072  2100              MOVS     r1,#0
000074  2008              MOVS     r0,#8
000076  f7fffffe          BL       RCC_APB1PeriphResetCmd
00007a  e094              B        |L1.422|
                  |L1.124|
;;;151      } 
;;;152      else if (TIMx == TIM6)
00007c  48e5              LDR      r0,|L1.1044|
00007e  4284              CMP      r4,r0
000080  d108              BNE      |L1.148|
;;;153      {
;;;154        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
000082  2101              MOVS     r1,#1
000084  2010              MOVS     r0,#0x10
000086  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;155        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
00008a  2100              MOVS     r1,#0
00008c  2010              MOVS     r0,#0x10
00008e  f7fffffe          BL       RCC_APB1PeriphResetCmd
000092  e088              B        |L1.422|
                  |L1.148|
;;;156      } 
;;;157      else if (TIMx == TIM7)
000094  48e0              LDR      r0,|L1.1048|
000096  4284              CMP      r4,r0
000098  d108              BNE      |L1.172|
;;;158      {
;;;159        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
00009a  2101              MOVS     r1,#1
00009c  2020              MOVS     r0,#0x20
00009e  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;160        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
0000a2  2100              MOVS     r1,#0
0000a4  2020              MOVS     r0,#0x20
0000a6  f7fffffe          BL       RCC_APB1PeriphResetCmd
0000aa  e07c              B        |L1.422|
                  |L1.172|
;;;161      } 
;;;162      else if (TIMx == TIM8)
0000ac  48db              LDR      r0,|L1.1052|
0000ae  4284              CMP      r4,r0
0000b0  d108              BNE      |L1.196|
;;;163      {
;;;164        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
0000b2  2101              MOVS     r1,#1
0000b4  1440              ASRS     r0,r0,#17
0000b6  f7fffffe          BL       RCC_APB2PeriphResetCmd
;;;165        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
0000ba  2100              MOVS     r1,#0
0000bc  1460              ASRS     r0,r4,#17
0000be  f7fffffe          BL       RCC_APB2PeriphResetCmd
0000c2  e070              B        |L1.422|
                  |L1.196|
;;;166      }
;;;167      else if (TIMx == TIM9)
0000c4  48d6              LDR      r0,|L1.1056|
0000c6  4284              CMP      r4,r0
0000c8  d109              BNE      |L1.222|
;;;168      {      
;;;169        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
0000ca  2101              MOVS     r1,#1
0000cc  04c8              LSLS     r0,r1,#19
0000ce  f7fffffe          BL       RCC_APB2PeriphResetCmd
;;;170        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);  
0000d2  2100              MOVS     r1,#0
0000d4  f44f2000          MOV      r0,#0x80000
0000d8  f7fffffe          BL       RCC_APB2PeriphResetCmd
0000dc  e063              B        |L1.422|
                  |L1.222|
;;;171       }  
;;;172      else if (TIMx == TIM10)
0000de  48d1              LDR      r0,|L1.1060|
0000e0  4284              CMP      r4,r0
0000e2  d109              BNE      |L1.248|
;;;173      {      
;;;174        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
0000e4  2101              MOVS     r1,#1
0000e6  0508              LSLS     r0,r1,#20
0000e8  f7fffffe          BL       RCC_APB2PeriphResetCmd
;;;175        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);  
0000ec  2100              MOVS     r1,#0
0000ee  f44f1080          MOV      r0,#0x100000
0000f2  f7fffffe          BL       RCC_APB2PeriphResetCmd
0000f6  e056              B        |L1.422|
                  |L1.248|
;;;176      }  
;;;177      else if (TIMx == TIM11) 
0000f8  48cb              LDR      r0,|L1.1064|
0000fa  4284              CMP      r4,r0
0000fc  d109              BNE      |L1.274|
;;;178      {     
;;;179        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
0000fe  2101              MOVS     r1,#1
000100  0548              LSLS     r0,r1,#21
000102  f7fffffe          BL       RCC_APB2PeriphResetCmd
;;;180        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);  
000106  2100              MOVS     r1,#0
000108  f44f1000          MOV      r0,#0x200000
00010c  f7fffffe          BL       RCC_APB2PeriphResetCmd
000110  e049              B        |L1.422|
                  |L1.274|
;;;181      }  
;;;182      else if (TIMx == TIM12)
000112  48c6              LDR      r0,|L1.1068|
000114  4284              CMP      r4,r0
000116  d108              BNE      |L1.298|
;;;183      {      
;;;184        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
000118  2101              MOVS     r1,#1
00011a  2040              MOVS     r0,#0x40
00011c  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;185        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);  
000120  2100              MOVS     r1,#0
000122  2040              MOVS     r0,#0x40
000124  f7fffffe          BL       RCC_APB1PeriphResetCmd
000128  e03d              B        |L1.422|
                  |L1.298|
;;;186      }  
;;;187      else if (TIMx == TIM13) 
00012a  48c1              LDR      r0,|L1.1072|
00012c  4284              CMP      r4,r0
00012e  d108              BNE      |L1.322|
;;;188      {       
;;;189        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
000130  2101              MOVS     r1,#1
000132  2080              MOVS     r0,#0x80
000134  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;190        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);  
000138  2100              MOVS     r1,#0
00013a  2080              MOVS     r0,#0x80
00013c  f7fffffe          BL       RCC_APB1PeriphResetCmd
000140  e031              B        |L1.422|
                  |L1.322|
;;;191      }
;;;192      else if (TIMx == TIM14) 
000142  48bc              LDR      r0,|L1.1076|
000144  4284              CMP      r4,r0
000146  d108              BNE      |L1.346|
;;;193      {       
;;;194        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
000148  2101              MOVS     r1,#1
00014a  1580              ASRS     r0,r0,#22
00014c  f7fffffe          BL       RCC_APB1PeriphResetCmd
;;;195        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);  
000150  2100              MOVS     r1,#0
000152  15a0              ASRS     r0,r4,#22
000154  f7fffffe          BL       RCC_APB1PeriphResetCmd
000158  e025              B        |L1.422|
                  |L1.346|
;;;196      }        
;;;197      else if (TIMx == TIM15)
00015a  48b7              LDR      r0,|L1.1080|
00015c  4284              CMP      r4,r0
00015e  d109              BNE      |L1.372|
;;;198      {
;;;199        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);
000160  2101              MOVS     r1,#1
000162  0408              LSLS     r0,r1,#16
000164  f7fffffe          BL       RCC_APB2PeriphResetCmd
;;;200        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);
000168  2100              MOVS     r1,#0
00016a  f44f3080          MOV      r0,#0x10000
00016e  f7fffffe          BL       RCC_APB2PeriphResetCmd
000172  e018              B        |L1.422|
                  |L1.372|
;;;201      } 
;;;202      else if (TIMx == TIM16)
000174  48b1              LDR      r0,|L1.1084|
000176  4284              CMP      r4,r0
000178  d109              BNE      |L1.398|
;;;203      {
;;;204        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);
00017a  2101              MOVS     r1,#1
00017c  0448              LSLS     r0,r1,#17
00017e  f7fffffe          BL       RCC_APB2PeriphResetCmd
;;;205        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);
000182  2100              MOVS     r1,#0
000184  f44f3000          MOV      r0,#0x20000
000188  f7fffffe          BL       RCC_APB2PeriphResetCmd
00018c  e00b              B        |L1.422|
                  |L1.398|
;;;206      } 
;;;207      else
;;;208      {
;;;209        if (TIMx == TIM17)
00018e  48ac              LDR      r0,|L1.1088|
000190  4284              CMP      r4,r0
000192  d108              BNE      |L1.422|
;;;210        {
;;;211          RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);
000194  2101              MOVS     r1,#1
000196  0488              LSLS     r0,r1,#18
000198  f7fffffe          BL       RCC_APB2PeriphResetCmd
;;;212          RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);
00019c  2100              MOVS     r1,#0
00019e  f44f2080          MOV      r0,#0x40000
0001a2  f7fffffe          BL       RCC_APB2PeriphResetCmd
                  |L1.422|
;;;213        }  
;;;214      }
;;;215    }
0001a6  bd10              POP      {r4,pc}
;;;216    
                          ENDP

                  TIM_TimeBaseInit PROC
;;;225      */
;;;226    void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
0001a8  2200              MOVS     r2,#0
;;;227    {
;;;228      uint16_t tmpcr1 = 0;
;;;229    
;;;230      /* Check the parameters */
;;;231      assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
;;;232      assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
;;;233      assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
;;;234    
;;;235      tmpcr1 = TIMx->CR1;  
0001aa  8802              LDRH     r2,[r0,#0]
;;;236    
;;;237      if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)||
0001ac  4b95              LDR      r3,|L1.1028|
0001ae  4298              CMP      r0,r3
0001b0  d00e              BEQ      |L1.464|
0001b2  4b9a              LDR      r3,|L1.1052|
0001b4  4298              CMP      r0,r3
0001b6  d00b              BEQ      |L1.464|
0001b8  f1b04f80          CMP      r0,#0x40000000
0001bc  d008              BEQ      |L1.464|
0001be  4b92              LDR      r3,|L1.1032|
0001c0  4298              CMP      r0,r3
0001c2  d005              BEQ      |L1.464|
;;;238         (TIMx == TIM4) || (TIMx == TIM5)) 
0001c4  4b91              LDR      r3,|L1.1036|
0001c6  4298              CMP      r0,r3
0001c8  d002              BEQ      |L1.464|
0001ca  4b91              LDR      r3,|L1.1040|
0001cc  4298              CMP      r0,r3
0001ce  d104              BNE      |L1.474|
                  |L1.464|
;;;239      {
;;;240        /* Select the Counter Mode */
;;;241        tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
0001d0  f64f738f          MOV      r3,#0xff8f
0001d4  401a              ANDS     r2,r2,r3
;;;242        tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
0001d6  884b              LDRH     r3,[r1,#2]
0001d8  431a              ORRS     r2,r2,r3
                  |L1.474|
;;;243      }
;;;244     
;;;245      if((TIMx != TIM6) && (TIMx != TIM7))
0001da  4b8e              LDR      r3,|L1.1044|
0001dc  4298              CMP      r0,r3
0001de  d007              BEQ      |L1.496|
0001e0  4b8d              LDR      r3,|L1.1048|
0001e2  4298              CMP      r0,r3
0001e4  d004              BEQ      |L1.496|
;;;246      {
;;;247        /* Set the clock division */
;;;248        tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
0001e6  f64f43ff          MOV      r3,#0xfcff
0001ea  401a              ANDS     r2,r2,r3
;;;249        tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
0001ec  88cb              LDRH     r3,[r1,#6]
0001ee  431a              ORRS     r2,r2,r3
                  |L1.496|
;;;250      }
;;;251    
;;;252      TIMx->CR1 = tmpcr1;
0001f0  8002              STRH     r2,[r0,#0]
;;;253    
;;;254      /* Set the Autoreload value */
;;;255      TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
0001f2  888b              LDRH     r3,[r1,#4]
0001f4  8583              STRH     r3,[r0,#0x2c]
;;;256     
;;;257      /* Set the Prescaler value */
;;;258      TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
0001f6  880b              LDRH     r3,[r1,#0]
0001f8  8503              STRH     r3,[r0,#0x28]
;;;259        
;;;260      if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17))  
0001fa  4b82              LDR      r3,|L1.1028|
0001fc  4298              CMP      r0,r3
0001fe  d00b              BEQ      |L1.536|
000200  4b86              LDR      r3,|L1.1052|
000202  4298              CMP      r0,r3
000204  d008              BEQ      |L1.536|
000206  4b8c              LDR      r3,|L1.1080|
000208  4298              CMP      r0,r3
00020a  d005              BEQ      |L1.536|
00020c  4b8b              LDR      r3,|L1.1084|
00020e  4298              CMP      r0,r3
000210  d002              BEQ      |L1.536|
000212  4b8b              LDR      r3,|L1.1088|
000214  4298              CMP      r0,r3
000216  d101              BNE      |L1.540|
                  |L1.536|
;;;261      {
;;;262        /* Set the Repetition Counter value */
;;;263        TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
000218  7a0b              LDRB     r3,[r1,#8]
00021a  8603              STRH     r3,[r0,#0x30]
                  |L1.540|
;;;264      }
;;;265    
;;;266      /* Generate an update event to reload the Prescaler and the Repetition counter
;;;267         values immediately */
;;;268      TIMx->EGR = TIM_PSCReloadMode_Immediate;           
00021c  2301              MOVS     r3,#1
00021e  8283              STRH     r3,[r0,#0x14]
;;;269    }
000220  4770              BX       lr
;;;270    
                          ENDP

                  TIM_OC1Init PROC
;;;278      */
;;;279    void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
000222  b570              PUSH     {r4-r6,lr}
;;;280    {
;;;281      uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
000224  2200              MOVS     r2,#0
000226  2300              MOVS     r3,#0
000228  2400              MOVS     r4,#0
;;;282       
;;;283      /* Check the parameters */
;;;284      assert_param(IS_TIM_LIST8_PERIPH(TIMx));
;;;285      assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
;;;286      assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
;;;287      assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
;;;288     /* Disable the Channel 1: Reset the CC1E Bit */
;;;289      TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
00022a  8c05              LDRH     r5,[r0,#0x20]
00022c  f64f76fe          MOV      r6,#0xfffe
000230  4035              ANDS     r5,r5,r6
000232  8405              STRH     r5,[r0,#0x20]
;;;290      /* Get the TIMx CCER register value */
;;;291      tmpccer = TIMx->CCER;
000234  8c03              LDRH     r3,[r0,#0x20]
;;;292      /* Get the TIMx CR2 register value */
;;;293      tmpcr2 =  TIMx->CR2;
000236  8884              LDRH     r4,[r0,#4]
;;;294      
;;;295      /* Get the TIMx CCMR1 register value */
;;;296      tmpccmrx = TIMx->CCMR1;
000238  8b02              LDRH     r2,[r0,#0x18]
;;;297        
;;;298      /* Reset the Output Compare Mode Bits */
;;;299      tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
00023a  f64f758f          MOV      r5,#0xff8f
00023e  402a              ANDS     r2,r2,r5
;;;300      tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
000240  1eb5              SUBS     r5,r6,#2
000242  402a              ANDS     r2,r2,r5
;;;301    
;;;302      /* Select the Output Compare Mode */
;;;303      tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
000244  880d              LDRH     r5,[r1,#0]
000246  432a              ORRS     r2,r2,r5
;;;304      
;;;305      /* Reset the Output Polarity level */
;;;306      tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
000248  1e75              SUBS     r5,r6,#1
00024a  402b              ANDS     r3,r3,r5
;;;307      /* Set the Output Compare Polarity */
;;;308      tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
00024c  890d              LDRH     r5,[r1,#8]
00024e  432b              ORRS     r3,r3,r5
;;;309      
;;;310      /* Set the Output State */
;;;311      tmpccer |= TIM_OCInitStruct->TIM_OutputState;
000250  884d              LDRH     r5,[r1,#2]
000252  432b              ORRS     r3,r3,r5
;;;312        
;;;313      if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)||
000254  4d6b              LDR      r5,|L1.1028|
000256  42a8              CMP      r0,r5
000258  d00b              BEQ      |L1.626|
00025a  4d70              LDR      r5,|L1.1052|
00025c  42a8              CMP      r0,r5
00025e  d008              BEQ      |L1.626|
000260  4d75              LDR      r5,|L1.1080|
000262  42a8              CMP      r0,r5
000264  d005              BEQ      |L1.626|
;;;314         (TIMx == TIM16)|| (TIMx == TIM17))
000266  4d75              LDR      r5,|L1.1084|
000268  42a8              CMP      r0,r5
00026a  d002              BEQ      |L1.626|
00026c  4d74              LDR      r5,|L1.1088|
00026e  42a8              CMP      r0,r5
000270  d113              BNE      |L1.666|
                  |L1.626|
;;;315      {
;;;316        assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
;;;317        assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
;;;318        assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
;;;319        assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
;;;320        
;;;321        /* Reset the Output N Polarity level */
;;;322        tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));
000272  f64f75f7          MOV      r5,#0xfff7
000276  402b              ANDS     r3,r3,r5
;;;323        /* Set the Output N Polarity */
;;;324        tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
000278  894d              LDRH     r5,[r1,#0xa]
00027a  432b              ORRS     r3,r3,r5
;;;325        
;;;326        /* Reset the Output N State */
;;;327        tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE));    
00027c  f64f75fb          MOV      r5,#0xfffb
000280  402b              ANDS     r3,r3,r5
;;;328        /* Set the Output N State */
;;;329        tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
000282  888d              LDRH     r5,[r1,#4]
000284  432b              ORRS     r3,r3,r5
;;;330        
;;;331        /* Reset the Output Compare and Output Compare N IDLE State */
;;;332        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));
000286  f64f65ff          MOV      r5,#0xfeff
00028a  402c              ANDS     r4,r4,r5
;;;333        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));
00028c  f64f55ff          MOV      r5,#0xfdff
000290  402c              ANDS     r4,r4,r5
;;;334        
;;;335        /* Set the Output Idle state */
;;;336        tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
000292  898d              LDRH     r5,[r1,#0xc]
000294  432c              ORRS     r4,r4,r5
;;;337        /* Set the Output N Idle state */
;;;338        tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
000296  89cd              LDRH     r5,[r1,#0xe]
000298  432c              ORRS     r4,r4,r5
                  |L1.666|
;;;339      }
;;;340      /* Write to TIMx CR2 */
;;;341      TIMx->CR2 = tmpcr2;
00029a  8084              STRH     r4,[r0,#4]
;;;342      
;;;343      /* Write to TIMx CCMR1 */
;;;344      TIMx->CCMR1 = tmpccmrx;
00029c  8302              STRH     r2,[r0,#0x18]
;;;345    
;;;346      /* Set the Capture Compare Register value */
;;;347      TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; 
00029e  88cd              LDRH     r5,[r1,#6]
0002a0  8685              STRH     r5,[r0,#0x34]
;;;348     
;;;349      /* Write to TIMx CCER */
;;;350      TIMx->CCER = tmpccer;
0002a2  8403              STRH     r3,[r0,#0x20]
;;;351    }
0002a4  bd70              POP      {r4-r6,pc}
;;;352    
                          ENDP

                  TIM_OC2Init PROC
;;;361      */
;;;362    void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
0002a6  b570              PUSH     {r4-r6,lr}
;;;363    {
;;;364      uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
0002a8  2200              MOVS     r2,#0
0002aa  2300              MOVS     r3,#0
0002ac  2400              MOVS     r4,#0
;;;365       
;;;366      /* Check the parameters */
;;;367      assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 
;;;368      assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
;;;369      assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
;;;370      assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
;;;371       /* Disable the Channel 2: Reset the CC2E Bit */
;;;372      TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
0002ae  8c05              LDRH     r5,[r0,#0x20]
0002b0  f64f76ef          MOV      r6,#0xffef
0002b4  4035              ANDS     r5,r5,r6
0002b6  8405              STRH     r5,[r0,#0x20]
;;;373      
;;;374      /* Get the TIMx CCER register value */  
;;;375      tmpccer = TIMx->CCER;
0002b8  8c03              LDRH     r3,[r0,#0x20]
;;;376      /* Get the TIMx CR2 register value */
;;;377      tmpcr2 =  TIMx->CR2;
0002ba  8884              LDRH     r4,[r0,#4]
;;;378      
;;;379      /* Get the TIMx CCMR1 register value */
;;;380      tmpccmrx = TIMx->CCMR1;
0002bc  8b02              LDRH     r2,[r0,#0x18]
;;;381        
;;;382      /* Reset the Output Compare mode and Capture/Compare selection Bits */
;;;383      tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
0002be  f64875ff          MOV      r5,#0x8fff
0002c2  402a              ANDS     r2,r2,r5
;;;384      tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));
0002c4  f64f45ff          MOV      r5,#0xfcff
0002c8  402a              ANDS     r2,r2,r5
;;;385      
;;;386      /* Select the Output Compare Mode */
;;;387      tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
0002ca  880d              LDRH     r5,[r1,#0]
0002cc  062d              LSLS     r5,r5,#24
0002ce  ea424215          ORR      r2,r2,r5,LSR #16
;;;388      
;;;389      /* Reset the Output Polarity level */
;;;390      tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
0002d2  f64f75df          MOV      r5,#0xffdf
0002d6  402b              ANDS     r3,r3,r5
;;;391      /* Set the Output Compare Polarity */
;;;392      tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
0002d8  890d              LDRH     r5,[r1,#8]
0002da  052d              LSLS     r5,r5,#20
0002dc  ea434315          ORR      r3,r3,r5,LSR #16
;;;393      
;;;394      /* Set the Output State */
;;;395      tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
0002e0  884d              LDRH     r5,[r1,#2]
0002e2  052d              LSLS     r5,r5,#20
0002e4  ea434315          ORR      r3,r3,r5,LSR #16
;;;396        
;;;397      if((TIMx == TIM1) || (TIMx == TIM8))
0002e8  4d46              LDR      r5,|L1.1028|
0002ea  42a8              CMP      r0,r5
0002ec  d002              BEQ      |L1.756|
0002ee  4d4b              LDR      r5,|L1.1052|
0002f0  42a8              CMP      r0,r5
0002f2  d11b              BNE      |L1.812|
                  |L1.756|
;;;398      {
;;;399        assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
;;;400        assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
;;;401        assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
;;;402        assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
;;;403        
;;;404        /* Reset the Output N Polarity level */
;;;405        tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));
0002f4  f64f757f          MOV      r5,#0xff7f
0002f8  402b              ANDS     r3,r3,r5
;;;406        /* Set the Output N Polarity */
;;;407        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
0002fa  894d              LDRH     r5,[r1,#0xa]
0002fc  052d              LSLS     r5,r5,#20
0002fe  ea434315          ORR      r3,r3,r5,LSR #16
;;;408        
;;;409        /* Reset the Output N State */
;;;410        tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE));    
000302  f64f75bf          MOV      r5,#0xffbf
000306  402b              ANDS     r3,r3,r5
;;;411        /* Set the Output N State */
;;;412        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
000308  888d              LDRH     r5,[r1,#4]
00030a  052d              LSLS     r5,r5,#20
00030c  ea434315          ORR      r3,r3,r5,LSR #16
;;;413        
;;;414        /* Reset the Output Compare and Output Compare N IDLE State */
;;;415        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));
000310  f64f35ff          MOV      r5,#0xfbff
000314  402c              ANDS     r4,r4,r5
;;;416        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));
000316  f24f75ff          MOV      r5,#0xf7ff
00031a  402c              ANDS     r4,r4,r5
;;;417        
;;;418        /* Set the Output Idle state */
;;;419        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
00031c  898d              LDRH     r5,[r1,#0xc]
00031e  04ad              LSLS     r5,r5,#18
000320  ea444415          ORR      r4,r4,r5,LSR #16
;;;420        /* Set the Output N Idle state */
;;;421        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
000324  89cd              LDRH     r5,[r1,#0xe]
000326  04ad              LSLS     r5,r5,#18
000328  ea444415          ORR      r4,r4,r5,LSR #16
                  |L1.812|
;;;422      }
;;;423      /* Write to TIMx CR2 */
;;;424      TIMx->CR2 = tmpcr2;
00032c  8084              STRH     r4,[r0,#4]
;;;425      
;;;426      /* Write to TIMx CCMR1 */
;;;427      TIMx->CCMR1 = tmpccmrx;
00032e  8302              STRH     r2,[r0,#0x18]
;;;428    
;;;429      /* Set the Capture Compare Register value */
;;;430      TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
000330  88cd              LDRH     r5,[r1,#6]
000332  8705              STRH     r5,[r0,#0x38]
;;;431      
;;;432      /* Write to TIMx CCER */
;;;433      TIMx->CCER = tmpccer;
000334  8403              STRH     r3,[r0,#0x20]
;;;434    }
000336  bd70              POP      {r4-r6,pc}
;;;435    
                          ENDP

                  TIM_OC3Init PROC
;;;443      */
;;;444    void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
000338  b570              PUSH     {r4-r6,lr}
;;;445    {
;;;446      uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
00033a  2200              MOVS     r2,#0
00033c  2300              MOVS     r3,#0
00033e  2400              MOVS     r4,#0
;;;447       
;;;448      /* Check the parameters */
;;;449      assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
;;;450      assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
;;;451      assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
;;;452      assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
;;;453      /* Disable the Channel 2: Reset the CC2E Bit */
;;;454      TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
000340  8c05              LDRH     r5,[r0,#0x20]
000342  f64f66ff          MOV      r6,#0xfeff
000346  4035              ANDS     r5,r5,r6
000348  8405              STRH     r5,[r0,#0x20]
;;;455      
;;;456      /* Get the TIMx CCER register value */
;;;457      tmpccer = TIMx->CCER;
00034a  8c03              LDRH     r3,[r0,#0x20]
;;;458      /* Get the TIMx CR2 register value */
;;;459      tmpcr2 =  TIMx->CR2;
00034c  8884              LDRH     r4,[r0,#4]
;;;460      
;;;461      /* Get the TIMx CCMR2 register value */
;;;462      tmpccmrx = TIMx->CCMR2;
00034e  8b82              LDRH     r2,[r0,#0x1c]
;;;463        
;;;464      /* Reset the Output Compare mode and Capture/Compare selection Bits */
;;;465      tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
000350  f64f758f          MOV      r5,#0xff8f
000354  402a              ANDS     r2,r2,r5
;;;466      tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S));  
000356  f64f75fc          MOV      r5,#0xfffc
00035a  402a              ANDS     r2,r2,r5
;;;467      /* Select the Output Compare Mode */
;;;468      tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
00035c  880d              LDRH     r5,[r1,#0]
00035e  432a              ORRS     r2,r2,r5
;;;469      
;;;470      /* Reset the Output Polarity level */
;;;471      tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
000360  f64f55ff          MOV      r5,#0xfdff
000364  402b              ANDS     r3,r3,r5
;;;472      /* Set the Output Compare Polarity */
;;;473      tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
000366  890d              LDRH     r5,[r1,#8]
000368  062d              LSLS     r5,r5,#24
00036a  ea434315          ORR      r3,r3,r5,LSR #16
;;;474      
;;;475      /* Set the Output State */
;;;476      tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
00036e  884d              LDRH     r5,[r1,#2]
000370  062d              LSLS     r5,r5,#24
000372  ea434315          ORR      r3,r3,r5,LSR #16
;;;477        
;;;478      if((TIMx == TIM1) || (TIMx == TIM8))
000376  4d23              LDR      r5,|L1.1028|
000378  42a8              CMP      r0,r5
00037a  d002              BEQ      |L1.898|
00037c  4d27              LDR      r5,|L1.1052|
00037e  42a8              CMP      r0,r5
000380  d11b              BNE      |L1.954|
                  |L1.898|
;;;479      {
;;;480        assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
;;;481        assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
;;;482        assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
;;;483        assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
;;;484        
;;;485        /* Reset the Output N Polarity level */
;;;486        tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));
000382  f24f75ff          MOV      r5,#0xf7ff
000386  402b              ANDS     r3,r3,r5
;;;487        /* Set the Output N Polarity */
;;;488        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
000388  894d              LDRH     r5,[r1,#0xa]
00038a  062d              LSLS     r5,r5,#24
00038c  ea434315          ORR      r3,r3,r5,LSR #16
;;;489        /* Reset the Output N State */
;;;490        tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));
000390  f64f35ff          MOV      r5,#0xfbff
000394  402b              ANDS     r3,r3,r5
;;;491        
;;;492        /* Set the Output N State */
;;;493        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
000396  888d              LDRH     r5,[r1,#4]
000398  062d              LSLS     r5,r5,#24
00039a  ea434315          ORR      r3,r3,r5,LSR #16
;;;494        /* Reset the Output Compare and Output Compare N IDLE State */
;;;495        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));
00039e  f64e75ff          MOV      r5,#0xefff
0003a2  402c              ANDS     r4,r4,r5
;;;496        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));
0003a4  f64d75ff          MOV      r5,#0xdfff
0003a8  402c              ANDS     r4,r4,r5
;;;497        /* Set the Output Idle state */
;;;498        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
0003aa  898d              LDRH     r5,[r1,#0xc]
0003ac  052d              LSLS     r5,r5,#20
0003ae  ea444415          ORR      r4,r4,r5,LSR #16
;;;499        /* Set the Output N Idle state */
;;;500        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
0003b2  89cd              LDRH     r5,[r1,#0xe]
0003b4  052d              LSLS     r5,r5,#20
0003b6  ea444415          ORR      r4,r4,r5,LSR #16
                  |L1.954|
;;;501      }
;;;502      /* Write to TIMx CR2 */
;;;503      TIMx->CR2 = tmpcr2;
0003ba  8084              STRH     r4,[r0,#4]
;;;504      
;;;505      /* Write to TIMx CCMR2 */
;;;506      TIMx->CCMR2 = tmpccmrx;
0003bc  8382              STRH     r2,[r0,#0x1c]
;;;507    
;;;508      /* Set the Capture Compare Register value */
;;;509      TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
0003be  88cd              LDRH     r5,[r1,#6]
0003c0  8785              STRH     r5,[r0,#0x3c]
;;;510      
;;;511      /* Write to TIMx CCER */
;;;512      TIMx->CCER = tmpccer;
0003c2  8403              STRH     r3,[r0,#0x20]
;;;513    }
0003c4  bd70              POP      {r4-r6,pc}
;;;514    
                          ENDP

                  TIM_OC4Init PROC
;;;522      */
;;;523    void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
0003c6  b570              PUSH     {r4-r6,lr}
;;;524    {
;;;525      uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
0003c8  2200              MOVS     r2,#0
0003ca  2300              MOVS     r3,#0
0003cc  2400              MOVS     r4,#0
;;;526       
;;;527      /* Check the parameters */
;;;528      assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
;;;529      assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
;;;530      assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
;;;531      assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
;;;532      /* Disable the Channel 2: Reset the CC4E Bit */
;;;533      TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
0003ce  8c05              LDRH     r5,[r0,#0x20]
0003d0  f64e76ff          MOV      r6,#0xefff
0003d4  4035              ANDS     r5,r5,r6
0003d6  8405              STRH     r5,[r0,#0x20]
;;;534      
;;;535      /* Get the TIMx CCER register value */
;;;536      tmpccer = TIMx->CCER;
0003d8  8c03              LDRH     r3,[r0,#0x20]
;;;537      /* Get the TIMx CR2 register value */
;;;538      tmpcr2 =  TIMx->CR2;
0003da  8884              LDRH     r4,[r0,#4]
;;;539      
;;;540      /* Get the TIMx CCMR2 register value */
;;;541      tmpccmrx = TIMx->CCMR2;
0003dc  8b82              LDRH     r2,[r0,#0x1c]
;;;542        
;;;543      /* Reset the Output Compare mode and Capture/Compare selection Bits */
;;;544      tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
0003de  f64875ff          MOV      r5,#0x8fff
0003e2  402a              ANDS     r2,r2,r5
;;;545      tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));
0003e4  f64f45ff          MOV      r5,#0xfcff
0003e8  402a              ANDS     r2,r2,r5
;;;546      
;;;547      /* Select the Output Compare Mode */
;;;548      tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
0003ea  880d              LDRH     r5,[r1,#0]
0003ec  062d              LSLS     r5,r5,#24
0003ee  ea424215          ORR      r2,r2,r5,LSR #16
;;;549      
;;;550      /* Reset the Output Polarity level */
;;;551      tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
0003f2  f64d75ff          MOV      r5,#0xdfff
0003f6  402b              ANDS     r3,r3,r5
;;;552      /* Set the Output Compare Polarity */
;;;553      tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
0003f8  890d              LDRH     r5,[r1,#8]
0003fa  072d              LSLS     r5,r5,#28
0003fc  ea434315          ORR      r3,r3,r5,LSR #16
;;;554      
;;;555      /* Set the Output State */
;;;556      tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
000400  884d              LDRH     r5,[r1,#2]
000402  e01f              B        |L1.1092|
                  |L1.1028|
                          DCD      0x40012c00
                  |L1.1032|
                          DCD      0x40000400
                  |L1.1036|
                          DCD      0x40000800
                  |L1.1040|
                          DCD      0x40000c00
                  |L1.1044|
                          DCD      0x40001000
                  |L1.1048|
                          DCD      0x40001400
                  |L1.1052|
                          DCD      0x40013400
                  |L1.1056|
                          DCD      0x40014c00
                  |L1.1060|
                          DCD      0x40015000
                  |L1.1064|
                          DCD      0x40015400
                  |L1.1068|
                          DCD      0x40001800
                  |L1.1072|
                          DCD      0x40001c00
                  |L1.1076|
                          DCD      0x40002000
                  |L1.1080|
                          DCD      0x40014000
                  |L1.1084|
                          DCD      0x40014400
                  |L1.1088|
                          DCD      0x40014800
                  |L1.1092|
000444  072d              LSLS     r5,r5,#28
000446  ea434315          ORR      r3,r3,r5,LSR #16
;;;557        
;;;558      if((TIMx == TIM1) || (TIMx == TIM8))
00044a  4df8              LDR      r5,|L1.2092|
00044c  42a8              CMP      r0,r5
00044e  d002              BEQ      |L1.1110|
000450  4df7              LDR      r5,|L1.2096|
000452  42a8              CMP      r0,r5
000454  d106              BNE      |L1.1124|
                  |L1.1110|
;;;559      {
;;;560        assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
;;;561        /* Reset the Output Compare IDLE State */
;;;562        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));
000456  f64b75ff          MOV      r5,#0xbfff
00045a  402c              ANDS     r4,r4,r5
;;;563        /* Set the Output Idle state */
;;;564        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
00045c  898d              LDRH     r5,[r1,#0xc]
00045e  05ad              LSLS     r5,r5,#22
000460  ea444415          ORR      r4,r4,r5,LSR #16
                  |L1.1124|
;;;565      }
;;;566      /* Write to TIMx CR2 */
;;;567      TIMx->CR2 = tmpcr2;
000464  8084              STRH     r4,[r0,#4]
;;;568      
;;;569      /* Write to TIMx CCMR2 */  
;;;570      TIMx->CCMR2 = tmpccmrx;
000466  8382              STRH     r2,[r0,#0x1c]
;;;571    
;;;572      /* Set the Capture Compare Register value */
;;;573      TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
000468  88cd              LDRH     r5,[r1,#6]
00046a  f8a05040          STRH     r5,[r0,#0x40]
;;;574      
;;;575      /* Write to TIMx CCER */
;;;576      TIMx->CCER = tmpccer;
00046e  8403              STRH     r3,[r0,#0x20]
;;;577    }
000470  bd70              POP      {r4-r6,pc}
;;;578    
                          ENDP

                  TIM_SetIC4Prescaler PROC
;;;2418     */
;;;2419   void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
000472  8b82              LDRH     r2,[r0,#0x1c]
;;;2420   {  
;;;2421     /* Check the parameters */
;;;2422     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;2423     assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
;;;2424     /* Reset the IC4PSC Bits */
;;;2425     TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);
000474  f24f33ff          MOV      r3,#0xf3ff
000478  401a              ANDS     r2,r2,r3
00047a  8382              STRH     r2,[r0,#0x1c]
;;;2426     /* Set the IC4PSC value */
;;;2427     TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
00047c  8b82              LDRH     r2,[r0,#0x1c]
00047e  060b              LSLS     r3,r1,#24
000480  ea424213          ORR      r2,r2,r3,LSR #16
000484  8382              STRH     r2,[r0,#0x1c]
;;;2428   }
000486  4770              BX       lr
;;;2429   
                          ENDP

                  TI4_Config PROC
;;;2844     */
;;;2845   static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
000488  b5f0              PUSH     {r4-r7,lr}
;;;2846                          uint16_t TIM_ICFilter)
;;;2847   {
;;;2848     uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
00048a  2400              MOVS     r4,#0
00048c  2500              MOVS     r5,#0
00048e  2600              MOVS     r6,#0
;;;2849   
;;;2850      /* Disable the Channel 4: Reset the CC4E Bit */
;;;2851     TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);
000490  8c07              LDRH     r7,[r0,#0x20]
000492  f64e7cff          MOV      r12,#0xefff
000496  ea07070c          AND      r7,r7,r12
00049a  8407              STRH     r7,[r0,#0x20]
;;;2852     tmpccmr2 = TIMx->CCMR2;
00049c  8b84              LDRH     r4,[r0,#0x1c]
;;;2853     tmpccer = TIMx->CCER;
00049e  8c05              LDRH     r5,[r0,#0x20]
;;;2854     tmp = (uint16_t)(TIM_ICPolarity << 12);
0004a0  070f              LSLS     r7,r1,#28
0004a2  0c3e              LSRS     r6,r7,#16
;;;2855     /* Select the Input and set the filter */
;;;2856     tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));
0004a4  f64047ff          MOV      r7,#0xcff
0004a8  403c              ANDS     r4,r4,r7
;;;2857     tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
0004aa  0617              LSLS     r7,r2,#24
0004ac  ea444417          ORR      r4,r4,r7,LSR #16
;;;2858     tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
0004b0  071f              LSLS     r7,r3,#28
0004b2  ea444417          ORR      r4,r4,r7,LSR #16
;;;2859     
;;;2860     if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
0004b6  4fdd              LDR      r7,|L1.2092|
0004b8  42b8              CMP      r0,r7
0004ba  d00e              BEQ      |L1.1242|
0004bc  4fdc              LDR      r7,|L1.2096|
0004be  42b8              CMP      r0,r7
0004c0  d00b              BEQ      |L1.1242|
0004c2  f1b04f80          CMP      r0,#0x40000000
0004c6  d008              BEQ      |L1.1242|
0004c8  4fda              LDR      r7,|L1.2100|
0004ca  42b8              CMP      r0,r7
0004cc  d005              BEQ      |L1.1242|
;;;2861        (TIMx == TIM4) ||(TIMx == TIM5))
0004ce  4fda              LDR      r7,|L1.2104|
0004d0  42b8              CMP      r0,r7
0004d2  d002              BEQ      |L1.1242|
0004d4  4fd9              LDR      r7,|L1.2108|
0004d6  42b8              CMP      r0,r7
0004d8  d106              BNE      |L1.1256|
                  |L1.1242|
;;;2862     {
;;;2863       /* Select the Polarity and set the CC4E Bit */
;;;2864       tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P));
0004da  f64d77ff          MOV      r7,#0xdfff
0004de  403d              ANDS     r5,r5,r7
;;;2865       tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
0004e0  f4465780          ORR      r7,r6,#0x1000
0004e4  433d              ORRS     r5,r5,r7
0004e6  e005              B        |L1.1268|
                  |L1.1256|
;;;2866     }
;;;2867     else
;;;2868     {
;;;2869       /* Select the Polarity and set the CC4E Bit */
;;;2870       tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP));
0004e8  f64757ff          MOV      r7,#0x7dff
0004ec  403d              ANDS     r5,r5,r7
;;;2871       tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E);
0004ee  f4415780          ORR      r7,r1,#0x1000
0004f2  433d              ORRS     r5,r5,r7
                  |L1.1268|
;;;2872     }
;;;2873     /* Write to TIMx CCMR2 and CCER registers */
;;;2874     TIMx->CCMR2 = tmpccmr2;
0004f4  8384              STRH     r4,[r0,#0x1c]
;;;2875     TIMx->CCER = tmpccer;
0004f6  8405              STRH     r5,[r0,#0x20]
;;;2876   }
0004f8  bdf0              POP      {r4-r7,pc}
;;;2877   
                          ENDP

                  TIM_SetIC3Prescaler PROC
;;;2396     */
;;;2397   void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
0004fa  8b82              LDRH     r2,[r0,#0x1c]
;;;2398   {
;;;2399     /* Check the parameters */
;;;2400     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;2401     assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
;;;2402     /* Reset the IC3PSC Bits */
;;;2403     TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);
0004fc  f64f73f3          MOV      r3,#0xfff3
000500  401a              ANDS     r2,r2,r3
000502  8382              STRH     r2,[r0,#0x1c]
;;;2404     /* Set the IC3PSC value */
;;;2405     TIMx->CCMR2 |= TIM_ICPSC;
000504  8b82              LDRH     r2,[r0,#0x1c]
000506  430a              ORRS     r2,r2,r1
000508  8382              STRH     r2,[r0,#0x1c]
;;;2406   }
00050a  4770              BX       lr
;;;2407   
                          ENDP

                  TI3_Config PROC
;;;2796     */
;;;2797   static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
00050c  b5f0              PUSH     {r4-r7,lr}
;;;2798                          uint16_t TIM_ICFilter)
;;;2799   {
;;;2800     uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
00050e  2400              MOVS     r4,#0
000510  2500              MOVS     r5,#0
000512  2600              MOVS     r6,#0
;;;2801     /* Disable the Channel 3: Reset the CC3E Bit */
;;;2802     TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);
000514  8c07              LDRH     r7,[r0,#0x20]
000516  f64f6cff          MOV      r12,#0xfeff
00051a  ea07070c          AND      r7,r7,r12
00051e  8407              STRH     r7,[r0,#0x20]
;;;2803     tmpccmr2 = TIMx->CCMR2;
000520  8b84              LDRH     r4,[r0,#0x1c]
;;;2804     tmpccer = TIMx->CCER;
000522  8c05              LDRH     r5,[r0,#0x20]
;;;2805     tmp = (uint16_t)(TIM_ICPolarity << 8);
000524  060f              LSLS     r7,r1,#24
000526  0c3e              LSRS     r6,r7,#16
;;;2806     /* Select the Input and set the filter */
;;;2807     tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));
000528  f64f770c          MOV      r7,#0xff0c
00052c  403c              ANDS     r4,r4,r7
;;;2808     tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
00052e  051f              LSLS     r7,r3,#20
000530  ea424717          ORR      r7,r2,r7,LSR #16
000534  433c              ORRS     r4,r4,r7
;;;2809       
;;;2810     if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
000536  4fbd              LDR      r7,|L1.2092|
000538  42b8              CMP      r0,r7
00053a  d00e              BEQ      |L1.1370|
00053c  4fbc              LDR      r7,|L1.2096|
00053e  42b8              CMP      r0,r7
000540  d00b              BEQ      |L1.1370|
000542  f1b04f80          CMP      r0,#0x40000000
000546  d008              BEQ      |L1.1370|
000548  4fba              LDR      r7,|L1.2100|
00054a  42b8              CMP      r0,r7
00054c  d005              BEQ      |L1.1370|
;;;2811        (TIMx == TIM4) ||(TIMx == TIM5))
00054e  4fba              LDR      r7,|L1.2104|
000550  42b8              CMP      r0,r7
000552  d002              BEQ      |L1.1370|
000554  4fb9              LDR      r7,|L1.2108|
000556  42b8              CMP      r0,r7
000558  d106              BNE      |L1.1384|
                  |L1.1370|
;;;2812     {
;;;2813       /* Select the Polarity and set the CC3E Bit */
;;;2814       tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P));
00055a  f64f57ff          MOV      r7,#0xfdff
00055e  403d              ANDS     r5,r5,r7
;;;2815       tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
000560  f4467780          ORR      r7,r6,#0x100
000564  433d              ORRS     r5,r5,r7
000566  e005              B        |L1.1396|
                  |L1.1384|
;;;2816     }
;;;2817     else
;;;2818     {
;;;2819       /* Select the Polarity and set the CC3E Bit */
;;;2820       tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));
000568  f24f57ff          MOV      r7,#0xf5ff
00056c  403d              ANDS     r5,r5,r7
;;;2821       tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E);
00056e  f4417780          ORR      r7,r1,#0x100
000572  433d              ORRS     r5,r5,r7
                  |L1.1396|
;;;2822     }
;;;2823     
;;;2824     /* Write to TIMx CCMR2 and CCER registers */
;;;2825     TIMx->CCMR2 = tmpccmr2;
000574  8384              STRH     r4,[r0,#0x1c]
;;;2826     TIMx->CCER = tmpccer;
000576  8405              STRH     r5,[r0,#0x20]
;;;2827   }
000578  bdf0              POP      {r4-r7,pc}
;;;2828   
                          ENDP

                  TIM_SetIC2Prescaler PROC
;;;2374     */
;;;2375   void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
00057a  8b02              LDRH     r2,[r0,#0x18]
;;;2376   {
;;;2377     /* Check the parameters */
;;;2378     assert_param(IS_TIM_LIST6_PERIPH(TIMx));
;;;2379     assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
;;;2380     /* Reset the IC2PSC Bits */
;;;2381     TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);
00057c  f24f33ff          MOV      r3,#0xf3ff
000580  401a              ANDS     r2,r2,r3
000582  8302              STRH     r2,[r0,#0x18]
;;;2382     /* Set the IC2PSC value */
;;;2383     TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
000584  8b02              LDRH     r2,[r0,#0x18]
000586  060b              LSLS     r3,r1,#24
000588  ea424213          ORR      r2,r2,r3,LSR #16
00058c  8302              STRH     r2,[r0,#0x18]
;;;2384   }
00058e  4770              BX       lr
;;;2385   
                          ENDP

                  TI2_Config PROC
;;;2747     */
;;;2748   static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
000590  b5f0              PUSH     {r4-r7,lr}
;;;2749                          uint16_t TIM_ICFilter)
;;;2750   {
;;;2751     uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
000592  2400              MOVS     r4,#0
000594  2500              MOVS     r5,#0
000596  2600              MOVS     r6,#0
;;;2752     /* Disable the Channel 2: Reset the CC2E Bit */
;;;2753     TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);
000598  8c07              LDRH     r7,[r0,#0x20]
00059a  f64f7cef          MOV      r12,#0xffef
00059e  ea07070c          AND      r7,r7,r12
0005a2  8407              STRH     r7,[r0,#0x20]
;;;2754     tmpccmr1 = TIMx->CCMR1;
0005a4  8b04              LDRH     r4,[r0,#0x18]
;;;2755     tmpccer = TIMx->CCER;
0005a6  8c05              LDRH     r5,[r0,#0x20]
;;;2756     tmp = (uint16_t)(TIM_ICPolarity << 4);
0005a8  050f              LSLS     r7,r1,#20
0005aa  0c3e              LSRS     r6,r7,#16
;;;2757     /* Select the Input and set the filter */
;;;2758     tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));
0005ac  f64047ff          MOV      r7,#0xcff
0005b0  403c              ANDS     r4,r4,r7
;;;2759     tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
0005b2  071f              LSLS     r7,r3,#28
0005b4  ea444417          ORR      r4,r4,r7,LSR #16
;;;2760     tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
0005b8  0617              LSLS     r7,r2,#24
0005ba  ea444417          ORR      r4,r4,r7,LSR #16
;;;2761     
;;;2762     if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
0005be  4f9b              LDR      r7,|L1.2092|
0005c0  42b8              CMP      r0,r7
0005c2  d00e              BEQ      |L1.1506|
0005c4  4f9a              LDR      r7,|L1.2096|
0005c6  42b8              CMP      r0,r7
0005c8  d00b              BEQ      |L1.1506|
0005ca  f1b04f80          CMP      r0,#0x40000000
0005ce  d008              BEQ      |L1.1506|
0005d0  4f98              LDR      r7,|L1.2100|
0005d2  42b8              CMP      r0,r7
0005d4  d005              BEQ      |L1.1506|
;;;2763        (TIMx == TIM4) ||(TIMx == TIM5))
0005d6  4f98              LDR      r7,|L1.2104|
0005d8  42b8              CMP      r0,r7
0005da  d002              BEQ      |L1.1506|
0005dc  4f97              LDR      r7,|L1.2108|
0005de  42b8              CMP      r0,r7
0005e0  d106              BNE      |L1.1520|
                  |L1.1506|
;;;2764     {
;;;2765       /* Select the Polarity and set the CC2E Bit */
;;;2766       tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P));
0005e2  f64f77df          MOV      r7,#0xffdf
0005e6  403d              ANDS     r5,r5,r7
;;;2767       tmpccer |=  (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
0005e8  f0460710          ORR      r7,r6,#0x10
0005ec  433d              ORRS     r5,r5,r7
0005ee  e005              B        |L1.1532|
                  |L1.1520|
;;;2768     }
;;;2769     else
;;;2770     {
;;;2771       /* Select the Polarity and set the CC2E Bit */
;;;2772       tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
0005f0  f64f775f          MOV      r7,#0xff5f
0005f4  403d              ANDS     r5,r5,r7
;;;2773       tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E);
0005f6  f0410710          ORR      r7,r1,#0x10
0005fa  433d              ORRS     r5,r5,r7
                  |L1.1532|
;;;2774     }
;;;2775     
;;;2776     /* Write to TIMx CCMR1 and CCER registers */
;;;2777     TIMx->CCMR1 = tmpccmr1 ;
0005fc  8304              STRH     r4,[r0,#0x18]
;;;2778     TIMx->CCER = tmpccer;
0005fe  8405              STRH     r5,[r0,#0x20]
;;;2779   }
000600  bdf0              POP      {r4-r7,pc}
;;;2780   
                          ENDP

                  TIM_SetIC1Prescaler PROC
;;;2352     */
;;;2353   void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
000602  8b02              LDRH     r2,[r0,#0x18]
;;;2354   {
;;;2355     /* Check the parameters */
;;;2356     assert_param(IS_TIM_LIST8_PERIPH(TIMx));
;;;2357     assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
;;;2358     /* Reset the IC1PSC Bits */
;;;2359     TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);
000604  f64f73f3          MOV      r3,#0xfff3
000608  401a              ANDS     r2,r2,r3
00060a  8302              STRH     r2,[r0,#0x18]
;;;2360     /* Set the IC1PSC value */
;;;2361     TIMx->CCMR1 |= TIM_ICPSC;
00060c  8b02              LDRH     r2,[r0,#0x18]
00060e  430a              ORRS     r2,r2,r1
000610  8302              STRH     r2,[r0,#0x18]
;;;2362   }
000612  4770              BX       lr
;;;2363   
                          ENDP

                  TI1_Config PROC
;;;2700     */
;;;2701   static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
000614  b5f0              PUSH     {r4-r7,lr}
;;;2702                          uint16_t TIM_ICFilter)
;;;2703   {
;;;2704     uint16_t tmpccmr1 = 0, tmpccer = 0;
000616  2400              MOVS     r4,#0
000618  2500              MOVS     r5,#0
;;;2705     /* Disable the Channel 1: Reset the CC1E Bit */
;;;2706     TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);
00061a  8c06              LDRH     r6,[r0,#0x20]
00061c  f64f77fe          MOV      r7,#0xfffe
000620  403e              ANDS     r6,r6,r7
000622  8406              STRH     r6,[r0,#0x20]
;;;2707     tmpccmr1 = TIMx->CCMR1;
000624  8b04              LDRH     r4,[r0,#0x18]
;;;2708     tmpccer = TIMx->CCER;
000626  8c05              LDRH     r5,[r0,#0x20]
;;;2709     /* Select the Input and set the filter */
;;;2710     tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));
000628  f64f760c          MOV      r6,#0xff0c
00062c  4034              ANDS     r4,r4,r6
;;;2711     tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
00062e  051e              LSLS     r6,r3,#20
000630  ea424616          ORR      r6,r2,r6,LSR #16
000634  4334              ORRS     r4,r4,r6
;;;2712     
;;;2713     if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
000636  4e7d              LDR      r6,|L1.2092|
000638  42b0              CMP      r0,r6
00063a  d00e              BEQ      |L1.1626|
00063c  4e7c              LDR      r6,|L1.2096|
00063e  42b0              CMP      r0,r6
000640  d00b              BEQ      |L1.1626|
000642  f1b04f80          CMP      r0,#0x40000000
000646  d008              BEQ      |L1.1626|
000648  4e7a              LDR      r6,|L1.2100|
00064a  42b0              CMP      r0,r6
00064c  d005              BEQ      |L1.1626|
;;;2714        (TIMx == TIM4) ||(TIMx == TIM5))
00064e  4e7a              LDR      r6,|L1.2104|
000650  42b0              CMP      r0,r6
000652  d002              BEQ      |L1.1626|
000654  4e79              LDR      r6,|L1.2108|
000656  42b0              CMP      r0,r6
000658  d106              BNE      |L1.1640|
                  |L1.1626|
;;;2715     {
;;;2716       /* Select the Polarity and set the CC1E Bit */
;;;2717       tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P));
00065a  f64f76fd          MOV      r6,#0xfffd
00065e  4035              ANDS     r5,r5,r6
;;;2718       tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
000660  f0410601          ORR      r6,r1,#1
000664  4335              ORRS     r5,r5,r6
000666  e005              B        |L1.1652|
                  |L1.1640|
;;;2719     }
;;;2720     else
;;;2721     {
;;;2722       /* Select the Polarity and set the CC1E Bit */
;;;2723       tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));
000668  f64f76f5          MOV      r6,#0xfff5
00066c  4035              ANDS     r5,r5,r6
;;;2724       tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
00066e  f0410601          ORR      r6,r1,#1
000672  4335              ORRS     r5,r5,r6
                  |L1.1652|
;;;2725     }
;;;2726   
;;;2727     /* Write to TIMx CCMR1 and CCER registers */
;;;2728     TIMx->CCMR1 = tmpccmr1;
000674  8304              STRH     r4,[r0,#0x18]
;;;2729     TIMx->CCER = tmpccer;
000676  8405              STRH     r5,[r0,#0x20]
;;;2730   }
000678  bdf0              POP      {r4-r7,pc}
;;;2731   
                          ENDP

                  TIM_ICInit PROC
;;;586      */
;;;587    void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
00067a  b570              PUSH     {r4-r6,lr}
;;;588    {
00067c  4604              MOV      r4,r0
00067e  460d              MOV      r5,r1
;;;589      /* Check the parameters */
;;;590      assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));  
;;;591      assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
;;;592      assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
;;;593      assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
;;;594      
;;;595      if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
000680  486a              LDR      r0,|L1.2092|
000682  4284              CMP      r4,r0
000684  d00e              BEQ      |L1.1700|
000686  486a              LDR      r0,|L1.2096|
000688  4284              CMP      r4,r0
00068a  d00b              BEQ      |L1.1700|
00068c  f1b44f80          CMP      r4,#0x40000000
000690  d008              BEQ      |L1.1700|
000692  4868              LDR      r0,|L1.2100|
000694  4284              CMP      r4,r0
000696  d005              BEQ      |L1.1700|
;;;596         (TIMx == TIM4) ||(TIMx == TIM5))
000698  4867              LDR      r0,|L1.2104|
00069a  4284              CMP      r4,r0
00069c  d002              BEQ      |L1.1700|
00069e  4867              LDR      r0,|L1.2108|
0006a0  4284              CMP      r4,r0
0006a2  d100              BNE      |L1.1702|
                  |L1.1700|
;;;597      {
;;;598        assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
0006a4  e000              B        |L1.1704|
                  |L1.1702|
;;;599      }
;;;600      else
;;;601      {
;;;602        assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity));
0006a6  bf00              NOP      
                  |L1.1704|
;;;603      }
;;;604      if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
0006a8  8828              LDRH     r0,[r5,#0]
0006aa  b950              CBNZ     r0,|L1.1730|
;;;605      {
;;;606        assert_param(IS_TIM_LIST8_PERIPH(TIMx));
;;;607        /* TI1 Configuration */
;;;608        TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
0006ac  892b              LDRH     r3,[r5,#8]
0006ae  88aa              LDRH     r2,[r5,#4]
0006b0  8869              LDRH     r1,[r5,#2]
0006b2  4620              MOV      r0,r4
0006b4  f7fffffe          BL       TI1_Config
;;;609                   TIM_ICInitStruct->TIM_ICSelection,
;;;610                   TIM_ICInitStruct->TIM_ICFilter);
;;;611        /* Set the Input Capture Prescaler value */
;;;612        TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
0006b8  88e9              LDRH     r1,[r5,#6]
0006ba  4620              MOV      r0,r4
0006bc  f7fffffe          BL       TIM_SetIC1Prescaler
0006c0  e025              B        |L1.1806|
                  |L1.1730|
;;;613      }
;;;614      else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
0006c2  8828              LDRH     r0,[r5,#0]
0006c4  2804              CMP      r0,#4
0006c6  d10a              BNE      |L1.1758|
;;;615      {
;;;616        assert_param(IS_TIM_LIST6_PERIPH(TIMx));
;;;617        /* TI2 Configuration */
;;;618        TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
0006c8  892b              LDRH     r3,[r5,#8]
0006ca  88aa              LDRH     r2,[r5,#4]
0006cc  8869              LDRH     r1,[r5,#2]
0006ce  4620              MOV      r0,r4
0006d0  f7fffffe          BL       TI2_Config
;;;619                   TIM_ICInitStruct->TIM_ICSelection,
;;;620                   TIM_ICInitStruct->TIM_ICFilter);
;;;621        /* Set the Input Capture Prescaler value */
;;;622        TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
0006d4  88e9              LDRH     r1,[r5,#6]
0006d6  4620              MOV      r0,r4
0006d8  f7fffffe          BL       TIM_SetIC2Prescaler
0006dc  e017              B        |L1.1806|
                  |L1.1758|
;;;623      }
;;;624      else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
0006de  8828              LDRH     r0,[r5,#0]
0006e0  2808              CMP      r0,#8
0006e2  d10a              BNE      |L1.1786|
;;;625      {
;;;626        assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;627        /* TI3 Configuration */
;;;628        TI3_Config(TIMx,  TIM_ICInitStruct->TIM_ICPolarity,
0006e4  892b              LDRH     r3,[r5,#8]
0006e6  88aa              LDRH     r2,[r5,#4]
0006e8  8869              LDRH     r1,[r5,#2]
0006ea  4620              MOV      r0,r4
0006ec  f7fffffe          BL       TI3_Config
;;;629                   TIM_ICInitStruct->TIM_ICSelection,
;;;630                   TIM_ICInitStruct->TIM_ICFilter);
;;;631        /* Set the Input Capture Prescaler value */
;;;632        TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
0006f0  88e9              LDRH     r1,[r5,#6]
0006f2  4620              MOV      r0,r4
0006f4  f7fffffe          BL       TIM_SetIC3Prescaler
0006f8  e009              B        |L1.1806|
                  |L1.1786|
;;;633      }
;;;634      else
;;;635      {
;;;636        assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;637        /* TI4 Configuration */
;;;638        TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
0006fa  892b              LDRH     r3,[r5,#8]
0006fc  88aa              LDRH     r2,[r5,#4]
0006fe  8869              LDRH     r1,[r5,#2]
000700  4620              MOV      r0,r4
000702  f7fffffe          BL       TI4_Config
;;;639                   TIM_ICInitStruct->TIM_ICSelection,
;;;640                   TIM_ICInitStruct->TIM_ICFilter);
;;;641        /* Set the Input Capture Prescaler value */
;;;642        TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
000706  88e9              LDRH     r1,[r5,#6]
000708  4620              MOV      r0,r4
00070a  f7fffffe          BL       TIM_SetIC4Prescaler
                  |L1.1806|
;;;643      }
;;;644    }
00070e  bd70              POP      {r4-r6,pc}
;;;645    
                          ENDP

                  TIM_PWMIConfig PROC
;;;653      */
;;;654    void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
000710  e92d41f0          PUSH     {r4-r8,lr}
;;;655    {
000714  4604              MOV      r4,r0
000716  460d              MOV      r5,r1
;;;656      uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
000718  2600              MOVS     r6,#0
;;;657      uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
00071a  2701              MOVS     r7,#1
;;;658      /* Check the parameters */
;;;659      assert_param(IS_TIM_LIST6_PERIPH(TIMx));
;;;660      /* Select the Opposite Input Polarity */
;;;661      if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
00071c  8868              LDRH     r0,[r5,#2]
00071e  b908              CBNZ     r0,|L1.1828|
;;;662      {
;;;663        icoppositepolarity = TIM_ICPolarity_Falling;
000720  2602              MOVS     r6,#2
000722  e000              B        |L1.1830|
                  |L1.1828|
;;;664      }
;;;665      else
;;;666      {
;;;667        icoppositepolarity = TIM_ICPolarity_Rising;
000724  2600              MOVS     r6,#0
                  |L1.1830|
;;;668      }
;;;669      /* Select the Opposite Input */
;;;670      if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
000726  88a8              LDRH     r0,[r5,#4]
000728  2801              CMP      r0,#1
00072a  d101              BNE      |L1.1840|
;;;671      {
;;;672        icoppositeselection = TIM_ICSelection_IndirectTI;
00072c  2702              MOVS     r7,#2
00072e  e000              B        |L1.1842|
                  |L1.1840|
;;;673      }
;;;674      else
;;;675      {
;;;676        icoppositeselection = TIM_ICSelection_DirectTI;
000730  2701              MOVS     r7,#1
                  |L1.1842|
;;;677      }
;;;678      if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
000732  8828              LDRH     r0,[r5,#0]
000734  b9a0              CBNZ     r0,|L1.1888|
;;;679      {
;;;680        /* TI1 Configuration */
;;;681        TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
000736  892b              LDRH     r3,[r5,#8]
000738  88aa              LDRH     r2,[r5,#4]
00073a  8869              LDRH     r1,[r5,#2]
00073c  4620              MOV      r0,r4
00073e  f7fffffe          BL       TI1_Config
;;;682                   TIM_ICInitStruct->TIM_ICFilter);
;;;683        /* Set the Input Capture Prescaler value */
;;;684        TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
000742  88e9              LDRH     r1,[r5,#6]
000744  4620              MOV      r0,r4
000746  f7fffffe          BL       TIM_SetIC1Prescaler
;;;685        /* TI2 Configuration */
;;;686        TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
00074a  892b              LDRH     r3,[r5,#8]
00074c  463a              MOV      r2,r7
00074e  4631              MOV      r1,r6
000750  4620              MOV      r0,r4
000752  f7fffffe          BL       TI2_Config
;;;687        /* Set the Input Capture Prescaler value */
;;;688        TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
000756  88e9              LDRH     r1,[r5,#6]
000758  4620              MOV      r0,r4
00075a  f7fffffe          BL       TIM_SetIC2Prescaler
00075e  e013              B        |L1.1928|
                  |L1.1888|
;;;689      }
;;;690      else
;;;691      { 
;;;692        /* TI2 Configuration */
;;;693        TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
000760  892b              LDRH     r3,[r5,#8]
000762  88aa              LDRH     r2,[r5,#4]
000764  8869              LDRH     r1,[r5,#2]
000766  4620              MOV      r0,r4
000768  f7fffffe          BL       TI2_Config
;;;694                   TIM_ICInitStruct->TIM_ICFilter);
;;;695        /* Set the Input Capture Prescaler value */
;;;696        TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
00076c  88e9              LDRH     r1,[r5,#6]
00076e  4620              MOV      r0,r4
000770  f7fffffe          BL       TIM_SetIC2Prescaler
;;;697        /* TI1 Configuration */
;;;698        TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
000774  892b              LDRH     r3,[r5,#8]
000776  463a              MOV      r2,r7
000778  4631              MOV      r1,r6
00077a  4620              MOV      r0,r4
00077c  f7fffffe          BL       TI1_Config
;;;699        /* Set the Input Capture Prescaler value */
;;;700        TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
000780  88e9              LDRH     r1,[r5,#6]
000782  4620              MOV      r0,r4
000784  f7fffffe          BL       TIM_SetIC1Prescaler
                  |L1.1928|
;;;701      }
;;;702    }
000788  e8bd81f0          POP      {r4-r8,pc}
;;;703    
                          ENDP

                  TIM_BDTRConfig PROC
;;;711      */
;;;712    void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
00078c  880a              LDRH     r2,[r1,#0]
;;;713    {
;;;714      /* Check the parameters */
;;;715      assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;716      assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
;;;717      assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
;;;718      assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
;;;719      assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
;;;720      assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
;;;721      assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
;;;722      /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
;;;723         the OSSI State, the dead time value and the Automatic Output Enable Bit */
;;;724      TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
00078e  884b              LDRH     r3,[r1,#2]
000790  431a              ORRS     r2,r2,r3
000792  888b              LDRH     r3,[r1,#4]
000794  431a              ORRS     r2,r2,r3
000796  88cb              LDRH     r3,[r1,#6]
000798  431a              ORRS     r2,r2,r3
00079a  890b              LDRH     r3,[r1,#8]
00079c  431a              ORRS     r2,r2,r3
00079e  894b              LDRH     r3,[r1,#0xa]
0007a0  431a              ORRS     r2,r2,r3
0007a2  898b              LDRH     r3,[r1,#0xc]
0007a4  431a              ORRS     r2,r2,r3
0007a6  f8a02044          STRH     r2,[r0,#0x44]
;;;725                 TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
;;;726                 TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
;;;727                 TIM_BDTRInitStruct->TIM_AutomaticOutput;
;;;728    }
0007aa  4770              BX       lr
;;;729    
                          ENDP

                  TIM_TimeBaseStructInit PROC
;;;735      */
;;;736    void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
0007ac  f64f71ff          MOV      r1,#0xffff
;;;737    {
;;;738      /* Set the default configuration */
;;;739      TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
0007b0  8081              STRH     r1,[r0,#4]
;;;740      TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
0007b2  2100              MOVS     r1,#0
0007b4  8001              STRH     r1,[r0,#0]
;;;741      TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
0007b6  80c1              STRH     r1,[r0,#6]
;;;742      TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
0007b8  8041              STRH     r1,[r0,#2]
;;;743      TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
0007ba  7201              STRB     r1,[r0,#8]
;;;744    }
0007bc  4770              BX       lr
;;;745    
                          ENDP

                  TIM_OCStructInit PROC
;;;751      */
;;;752    void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
0007be  2100              MOVS     r1,#0
;;;753    {
;;;754      /* Set the default configuration */
;;;755      TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
0007c0  8001              STRH     r1,[r0,#0]
;;;756      TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
0007c2  8041              STRH     r1,[r0,#2]
;;;757      TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
0007c4  8081              STRH     r1,[r0,#4]
;;;758      TIM_OCInitStruct->TIM_Pulse = 0x0000;
0007c6  80c1              STRH     r1,[r0,#6]
;;;759      TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
0007c8  8101              STRH     r1,[r0,#8]
;;;760      TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
0007ca  8141              STRH     r1,[r0,#0xa]
;;;761      TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
0007cc  8181              STRH     r1,[r0,#0xc]
;;;762      TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
0007ce  81c1              STRH     r1,[r0,#0xe]
;;;763    }
0007d0  4770              BX       lr
;;;764    
                          ENDP

                  TIM_ICStructInit PROC
;;;770      */
;;;771    void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
0007d2  2100              MOVS     r1,#0
;;;772    {
;;;773      /* Set the default configuration */
;;;774      TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
0007d4  8001              STRH     r1,[r0,#0]
;;;775      TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
0007d6  8041              STRH     r1,[r0,#2]
;;;776      TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
0007d8  2101              MOVS     r1,#1
0007da  8081              STRH     r1,[r0,#4]
;;;777      TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
0007dc  2100              MOVS     r1,#0
0007de  80c1              STRH     r1,[r0,#6]
;;;778      TIM_ICInitStruct->TIM_ICFilter = 0x00;
0007e0  8101              STRH     r1,[r0,#8]
;;;779    }
0007e2  4770              BX       lr
;;;780    
                          ENDP

                  TIM_BDTRStructInit PROC
;;;786      */
;;;787    void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
0007e4  2100              MOVS     r1,#0
;;;788    {
;;;789      /* Set the default configuration */
;;;790      TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
0007e6  8001              STRH     r1,[r0,#0]
;;;791      TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
0007e8  8041              STRH     r1,[r0,#2]
;;;792      TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
0007ea  8081              STRH     r1,[r0,#4]
;;;793      TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
0007ec  80c1              STRH     r1,[r0,#6]
;;;794      TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
0007ee  8101              STRH     r1,[r0,#8]
;;;795      TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
0007f0  8141              STRH     r1,[r0,#0xa]
;;;796      TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
0007f2  8181              STRH     r1,[r0,#0xc]
;;;797    }
0007f4  4770              BX       lr
;;;798    
                          ENDP

                  TIM_Cmd PROC
;;;805      */
;;;806    void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
0007f6  b121              CBZ      r1,|L1.2050|
;;;807    {
;;;808      /* Check the parameters */
;;;809      assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;810      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;811      
;;;812      if (NewState != DISABLE)
;;;813      {
;;;814        /* Enable the TIM Counter */
;;;815        TIMx->CR1 |= TIM_CR1_CEN;
0007f8  8802              LDRH     r2,[r0,#0]
0007fa  f0420201          ORR      r2,r2,#1
0007fe  8002              STRH     r2,[r0,#0]
000800  e004              B        |L1.2060|
                  |L1.2050|
;;;816      }
;;;817      else
;;;818      {
;;;819        /* Disable the TIM Counter */
;;;820        TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
000802  8802              LDRH     r2,[r0,#0]
000804  f64f73fe          MOV      r3,#0xfffe
000808  401a              ANDS     r2,r2,r3
00080a  8002              STRH     r2,[r0,#0]
                  |L1.2060|
;;;821      }
;;;822    }
00080c  4770              BX       lr
;;;823    
                          ENDP

                  TIM_CtrlPWMOutputs PROC
;;;830      */
;;;831    void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
00080e  b131              CBZ      r1,|L1.2078|
;;;832    {
;;;833      /* Check the parameters */
;;;834      assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;835      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;836      if (NewState != DISABLE)
;;;837      {
;;;838        /* Enable the TIM Main Output */
;;;839        TIMx->BDTR |= TIM_BDTR_MOE;
000810  f8b02044          LDRH     r2,[r0,#0x44]
000814  f4424200          ORR      r2,r2,#0x8000
000818  f8a02044          STRH     r2,[r0,#0x44]
00081c  e005              B        |L1.2090|
                  |L1.2078|
;;;840      }
;;;841      else
;;;842      {
;;;843        /* Disable the TIM Main Output */
;;;844        TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));
00081e  f8b02044          LDRH     r2,[r0,#0x44]
000822  f3c2020e          UBFX     r2,r2,#0,#15
000826  f8a02044          STRH     r2,[r0,#0x44]
                  |L1.2090|
;;;845      }  
;;;846    }
00082a  4770              BX       lr
                  |L1.2092|
                          DCD      0x40012c00
                  |L1.2096|
                          DCD      0x40013400
                  |L1.2100|
                          DCD      0x40000400
                  |L1.2104|
                          DCD      0x40000800
                  |L1.2108|
                          DCD      0x40000c00
                          ENDP

                  TIM_ITConfig PROC
;;;871      */
;;;872    void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
000840  b510              PUSH     {r4,lr}
;;;873    {  
;;;874      /* Check the parameters */
;;;875      assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;876      assert_param(IS_TIM_IT(TIM_IT));
;;;877      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;878      
;;;879      if (NewState != DISABLE)
000842  b11a              CBZ      r2,|L1.2124|
;;;880      {
;;;881        /* Enable the Interrupt sources */
;;;882        TIMx->DIER |= TIM_IT;
000844  8983              LDRH     r3,[r0,#0xc]
000846  430b              ORRS     r3,r3,r1
000848  8183              STRH     r3,[r0,#0xc]
00084a  e004              B        |L1.2134|
                  |L1.2124|
;;;883      }
;;;884      else
;;;885      {
;;;886        /* Disable the Interrupt sources */
;;;887        TIMx->DIER &= (uint16_t)~TIM_IT;
00084c  8983              LDRH     r3,[r0,#0xc]
00084e  43cc              MVNS     r4,r1
000850  b2a4              UXTH     r4,r4
000852  4023              ANDS     r3,r3,r4
000854  8183              STRH     r3,[r0,#0xc]
                  |L1.2134|
;;;888      }
;;;889    }
000856  bd10              POP      {r4,pc}
;;;890    
                          ENDP

                  TIM_GenerateEvent PROC
;;;908      */
;;;909    void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
000858  8281              STRH     r1,[r0,#0x14]
;;;910    { 
;;;911      /* Check the parameters */
;;;912      assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;913      assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
;;;914      
;;;915      /* Set the event sources */
;;;916      TIMx->EGR = TIM_EventSource;
;;;917    }
00085a  4770              BX       lr
;;;918    
                          ENDP

                  TIM_DMAConfig PROC
;;;936      */
;;;937    void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
00085c  ea410302          ORR      r3,r1,r2
;;;938    {
;;;939      /* Check the parameters */
;;;940      assert_param(IS_TIM_LIST4_PERIPH(TIMx));
;;;941      assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
;;;942      assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
;;;943      /* Set the DMA Base and the DMA Burst Length */
;;;944      TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
000860  f8a03048          STRH     r3,[r0,#0x48]
;;;945    }
000864  4770              BX       lr
;;;946    
                          ENDP

                  TIM_DMACmd PROC
;;;963      */
;;;964    void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
000866  b510              PUSH     {r4,lr}
;;;965    { 
;;;966      /* Check the parameters */
;;;967      assert_param(IS_TIM_LIST9_PERIPH(TIMx));
;;;968      assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
;;;969      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;970      
;;;971      if (NewState != DISABLE)
000868  b11a              CBZ      r2,|L1.2162|
;;;972      {
;;;973        /* Enable the DMA sources */
;;;974        TIMx->DIER |= TIM_DMASource; 
00086a  8983              LDRH     r3,[r0,#0xc]
00086c  430b              ORRS     r3,r3,r1
00086e  8183              STRH     r3,[r0,#0xc]
000870  e004              B        |L1.2172|
                  |L1.2162|
;;;975      }
;;;976      else
;;;977      {
;;;978        /* Disable the DMA sources */
;;;979        TIMx->DIER &= (uint16_t)~TIM_DMASource;
000872  8983              LDRH     r3,[r0,#0xc]
000874  43cc              MVNS     r4,r1
000876  b2a4              UXTH     r4,r4
000878  4023              ANDS     r3,r3,r4
00087a  8183              STRH     r3,[r0,#0xc]
                  |L1.2172|
;;;980      }
;;;981    }
00087c  bd10              POP      {r4,pc}
;;;982    
                          ENDP

                  TIM_InternalClockConfig PROC
;;;988      */
;;;989    void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
00087e  8901              LDRH     r1,[r0,#8]
;;;990    {
;;;991      /* Check the parameters */
;;;992      assert_param(IS_TIM_LIST6_PERIPH(TIMx));
;;;993      /* Disable slave mode to clock the prescaler directly with the internal clock */
;;;994      TIMx->SMCR &=  (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
000880  f64f72f8          MOV      r2,#0xfff8
000884  4011              ANDS     r1,r1,r2
000886  8101              STRH     r1,[r0,#8]
;;;995    }
000888  4770              BX       lr
;;;996    
                          ENDP

                  TIM_SelectInputTrigger PROC
;;;1228     */
;;;1229   void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
00088a  2200              MOVS     r2,#0
;;;1230   {
;;;1231     uint16_t tmpsmcr = 0;
;;;1232     /* Check the parameters */
;;;1233     assert_param(IS_TIM_LIST6_PERIPH(TIMx));
;;;1234     assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
;;;1235     /* Get the TIMx SMCR register value */
;;;1236     tmpsmcr = TIMx->SMCR;
00088c  8902              LDRH     r2,[r0,#8]
;;;1237     /* Reset the TS Bits */
;;;1238     tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
00088e  f64f738f          MOV      r3,#0xff8f
000892  401a              ANDS     r2,r2,r3
;;;1239     /* Set the Input Trigger source */
;;;1240     tmpsmcr |= TIM_InputTriggerSource;
000894  430a              ORRS     r2,r2,r1
;;;1241     /* Write to TIMx SMCR */
;;;1242     TIMx->SMCR = tmpsmcr;
000896  8102              STRH     r2,[r0,#8]
;;;1243   }
000898  4770              BX       lr
;;;1244   
                          ENDP

                  TIM_ITRxExternalClockConfig PROC
;;;1007     */
;;;1008   void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
00089a  b530              PUSH     {r4,r5,lr}
;;;1009   {
00089c  4604              MOV      r4,r0
00089e  460d              MOV      r5,r1
;;;1010     /* Check the parameters */
;;;1011     assert_param(IS_TIM_LIST6_PERIPH(TIMx));
;;;1012     assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
;;;1013     /* Select the Internal Trigger */
;;;1014     TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
0008a0  4629              MOV      r1,r5
0008a2  4620              MOV      r0,r4
0008a4  f7fffffe          BL       TIM_SelectInputTrigger
;;;1015     /* Select the External clock mode1 */
;;;1016     TIMx->SMCR |= TIM_SlaveMode_External1;
0008a8  8920              LDRH     r0,[r4,#8]
0008aa  f0400007          ORR      r0,r0,#7
0008ae  8120              STRH     r0,[r4,#8]
;;;1017   }
0008b0  bd30              POP      {r4,r5,pc}
;;;1018   
                          ENDP

                  TIM_TIxExternalClockConfig PROC
;;;1034     */
;;;1035   void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
0008b2  e92d41f0          PUSH     {r4-r8,lr}
;;;1036                                   uint16_t TIM_ICPolarity, uint16_t ICFilter)
;;;1037   {
0008b6  4604              MOV      r4,r0
0008b8  460d              MOV      r5,r1
0008ba  4616              MOV      r6,r2
0008bc  461f              MOV      r7,r3
;;;1038     /* Check the parameters */
;;;1039     assert_param(IS_TIM_LIST6_PERIPH(TIMx));
;;;1040     assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));
;;;1041     assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
;;;1042     assert_param(IS_TIM_IC_FILTER(ICFilter));
;;;1043     /* Configure the Timer Input Clock Source */
;;;1044     if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
0008be  2d60              CMP      r5,#0x60
0008c0  d106              BNE      |L1.2256|
;;;1045     {
;;;1046       TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
0008c2  463b              MOV      r3,r7
0008c4  2201              MOVS     r2,#1
0008c6  4631              MOV      r1,r6
0008c8  4620              MOV      r0,r4
0008ca  f7fffffe          BL       TI2_Config
0008ce  e005              B        |L1.2268|
                  |L1.2256|
;;;1047     }
;;;1048     else
;;;1049     {
;;;1050       TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
0008d0  463b              MOV      r3,r7
0008d2  2201              MOVS     r2,#1
0008d4  4631              MOV      r1,r6
0008d6  4620              MOV      r0,r4
0008d8  f7fffffe          BL       TI1_Config
                  |L1.2268|
;;;1051     }
;;;1052     /* Select the Trigger source */
;;;1053     TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
0008dc  4629              MOV      r1,r5
0008de  4620              MOV      r0,r4
0008e0  f7fffffe          BL       TIM_SelectInputTrigger
;;;1054     /* Select the External clock mode1 */
;;;1055     TIMx->SMCR |= TIM_SlaveMode_External1;
0008e4  8920              LDRH     r0,[r4,#8]
0008e6  f0400007          ORR      r0,r0,#7
0008ea  8120              STRH     r0,[r4,#8]
;;;1056   }
0008ec  e8bd81f0          POP      {r4-r8,pc}
;;;1057   
                          ENDP

                  TIM_ETRConfig PROC
;;;1147     */
;;;1148   void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
0008f0  b530              PUSH     {r4,r5,lr}
;;;1149                      uint16_t ExtTRGFilter)
;;;1150   {
;;;1151     uint16_t tmpsmcr = 0;
0008f2  2400              MOVS     r4,#0
;;;1152     /* Check the parameters */
;;;1153     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1154     assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
;;;1155     assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
;;;1156     assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
;;;1157     tmpsmcr = TIMx->SMCR;
0008f4  8904              LDRH     r4,[r0,#8]
;;;1158     /* Reset the ETR Bits */
;;;1159     tmpsmcr &= SMCR_ETR_Mask;
0008f6  b2e4              UXTB     r4,r4
;;;1160     /* Set the Prescaler, the Filter value and the Polarity */
;;;1161     tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
0008f8  061d              LSLS     r5,r3,#24
0008fa  ea424515          ORR      r5,r2,r5,LSR #16
0008fe  430d              ORRS     r5,r5,r1
000900  432c              ORRS     r4,r4,r5
;;;1162     /* Write to TIMx SMCR */
;;;1163     TIMx->SMCR = tmpsmcr;
000902  8104              STRH     r4,[r0,#8]
;;;1164   }
000904  bd30              POP      {r4,r5,pc}
;;;1165   
                          ENDP

                  TIM_ETRClockMode1Config PROC
;;;1074     */
;;;1075   void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
000906  e92d41f0          PUSH     {r4-r8,lr}
;;;1076                                uint16_t ExtTRGFilter)
;;;1077   {
00090a  4604              MOV      r4,r0
00090c  460d              MOV      r5,r1
00090e  4616              MOV      r6,r2
000910  4698              MOV      r8,r3
;;;1078     uint16_t tmpsmcr = 0;
000912  2700              MOVS     r7,#0
;;;1079     /* Check the parameters */
;;;1080     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1081     assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
;;;1082     assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
;;;1083     assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
;;;1084     /* Configure the ETR Clock source */
;;;1085     TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
000914  4643              MOV      r3,r8
000916  4632              MOV      r2,r6
000918  4629              MOV      r1,r5
00091a  4620              MOV      r0,r4
00091c  f7fffffe          BL       TIM_ETRConfig
;;;1086     
;;;1087     /* Get the TIMx SMCR register value */
;;;1088     tmpsmcr = TIMx->SMCR;
000920  8927              LDRH     r7,[r4,#8]
;;;1089     /* Reset the SMS Bits */
;;;1090     tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
000922  f64f70f8          MOV      r0,#0xfff8
000926  4007              ANDS     r7,r7,r0
;;;1091     /* Select the External clock mode1 */
;;;1092     tmpsmcr |= TIM_SlaveMode_External1;
000928  f0470707          ORR      r7,r7,#7
;;;1093     /* Select the Trigger selection : ETRF */
;;;1094     tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
00092c  f64f708f          MOV      r0,#0xff8f
000930  4007              ANDS     r7,r7,r0
;;;1095     tmpsmcr |= TIM_TS_ETRF;
000932  f0470770          ORR      r7,r7,#0x70
;;;1096     /* Write to TIMx SMCR */
;;;1097     TIMx->SMCR = tmpsmcr;
000936  8127              STRH     r7,[r4,#8]
;;;1098   }
000938  e8bd81f0          POP      {r4-r8,pc}
;;;1099   
                          ENDP

                  TIM_ETRClockMode2Config PROC
;;;1116     */
;;;1117   void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 
00093c  b5f0              PUSH     {r4-r7,lr}
;;;1118                                uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
;;;1119   {
00093e  4604              MOV      r4,r0
000940  460d              MOV      r5,r1
000942  4616              MOV      r6,r2
000944  461f              MOV      r7,r3
;;;1120     /* Check the parameters */
;;;1121     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1122     assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
;;;1123     assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
;;;1124     assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
;;;1125     /* Configure the ETR Clock source */
;;;1126     TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
000946  463b              MOV      r3,r7
000948  4632              MOV      r2,r6
00094a  4629              MOV      r1,r5
00094c  4620              MOV      r0,r4
00094e  f7fffffe          BL       TIM_ETRConfig
;;;1127     /* Enable the External clock mode2 */
;;;1128     TIMx->SMCR |= TIM_SMCR_ECE;
000952  8920              LDRH     r0,[r4,#8]
000954  f4404080          ORR      r0,r0,#0x4000
000958  8120              STRH     r0,[r4,#8]
;;;1129   }
00095a  bdf0              POP      {r4-r7,pc}
;;;1130   
                          ENDP

                  TIM_PrescalerConfig PROC
;;;1175     */
;;;1176   void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
00095c  8501              STRH     r1,[r0,#0x28]
;;;1177   {
;;;1178     /* Check the parameters */
;;;1179     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;1180     assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
;;;1181     /* Set the Prescaler value */
;;;1182     TIMx->PSC = Prescaler;
;;;1183     /* Set or reset the UG Bit */
;;;1184     TIMx->EGR = TIM_PSCReloadMode;
00095e  8282              STRH     r2,[r0,#0x14]
;;;1185   }
000960  4770              BX       lr
;;;1186   
                          ENDP

                  TIM_CounterModeConfig PROC
;;;1198     */
;;;1199   void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
000962  2200              MOVS     r2,#0
;;;1200   {
;;;1201     uint16_t tmpcr1 = 0;
;;;1202     /* Check the parameters */
;;;1203     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1204     assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
;;;1205     tmpcr1 = TIMx->CR1;
000964  8802              LDRH     r2,[r0,#0]
;;;1206     /* Reset the CMS and DIR Bits */
;;;1207     tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
000966  f64f738f          MOV      r3,#0xff8f
00096a  401a              ANDS     r2,r2,r3
;;;1208     /* Set the Counter Mode */
;;;1209     tmpcr1 |= TIM_CounterMode;
00096c  430a              ORRS     r2,r2,r1
;;;1210     /* Write to TIMx CR1 register */
;;;1211     TIMx->CR1 = tmpcr1;
00096e  8002              STRH     r2,[r0,#0]
;;;1212   }
000970  4770              BX       lr
;;;1213   
                          ENDP

                  TIM_EncoderInterfaceConfig PROC
;;;1263     */
;;;1264   void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
000972  b5f0              PUSH     {r4-r7,lr}
;;;1265                                   uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
;;;1266   {
;;;1267     uint16_t tmpsmcr = 0;
000974  2400              MOVS     r4,#0
;;;1268     uint16_t tmpccmr1 = 0;
000976  2500              MOVS     r5,#0
;;;1269     uint16_t tmpccer = 0;
000978  2600              MOVS     r6,#0
;;;1270       
;;;1271     /* Check the parameters */
;;;1272     assert_param(IS_TIM_LIST5_PERIPH(TIMx));
;;;1273     assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
;;;1274     assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
;;;1275     assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
;;;1276   
;;;1277     /* Get the TIMx SMCR register value */
;;;1278     tmpsmcr = TIMx->SMCR;
00097a  8904              LDRH     r4,[r0,#8]
;;;1279     
;;;1280     /* Get the TIMx CCMR1 register value */
;;;1281     tmpccmr1 = TIMx->CCMR1;
00097c  8b05              LDRH     r5,[r0,#0x18]
;;;1282     
;;;1283     /* Get the TIMx CCER register value */
;;;1284     tmpccer = TIMx->CCER;
00097e  8c06              LDRH     r6,[r0,#0x20]
;;;1285     
;;;1286     /* Set the encoder Mode */
;;;1287     tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
000980  f64f77f8          MOV      r7,#0xfff8
000984  403c              ANDS     r4,r4,r7
;;;1288     tmpsmcr |= TIM_EncoderMode;
000986  430c              ORRS     r4,r4,r1
;;;1289     
;;;1290     /* Select the Capture Compare 1 and the Capture Compare 2 as input */
;;;1291     tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
000988  f64f47fc          MOV      r7,#0xfcfc
00098c  403d              ANDS     r5,r5,r7
;;;1292     tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
00098e  f2401701          MOV      r7,#0x101
000992  433d              ORRS     r5,r5,r7
;;;1293     
;;;1294     /* Set the TI1 and the TI2 Polarities */
;;;1295     tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));
000994  f64f77dd          MOV      r7,#0xffdd
000998  403e              ANDS     r6,r6,r7
;;;1296     tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
00099a  051f              LSLS     r7,r3,#20
00099c  ea424717          ORR      r7,r2,r7,LSR #16
0009a0  433e              ORRS     r6,r6,r7
;;;1297     
;;;1298     /* Write to TIMx SMCR */
;;;1299     TIMx->SMCR = tmpsmcr;
0009a2  8104              STRH     r4,[r0,#8]
;;;1300     /* Write to TIMx CCMR1 */
;;;1301     TIMx->CCMR1 = tmpccmr1;
0009a4  8305              STRH     r5,[r0,#0x18]
;;;1302     /* Write to TIMx CCER */
;;;1303     TIMx->CCER = tmpccer;
0009a6  8406              STRH     r6,[r0,#0x20]
;;;1304   }
0009a8  bdf0              POP      {r4-r7,pc}
;;;1305   
                          ENDP

                  TIM_ForcedOC1Config PROC
;;;1314     */
;;;1315   void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
0009aa  2200              MOVS     r2,#0
;;;1316   {
;;;1317     uint16_t tmpccmr1 = 0;
;;;1318     /* Check the parameters */
;;;1319     assert_param(IS_TIM_LIST8_PERIPH(TIMx));
;;;1320     assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
;;;1321     tmpccmr1 = TIMx->CCMR1;
0009ac  8b02              LDRH     r2,[r0,#0x18]
;;;1322     /* Reset the OC1M Bits */
;;;1323     tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);
0009ae  f64f738f          MOV      r3,#0xff8f
0009b2  401a              ANDS     r2,r2,r3
;;;1324     /* Configure The Forced output Mode */
;;;1325     tmpccmr1 |= TIM_ForcedAction;
0009b4  430a              ORRS     r2,r2,r1
;;;1326     /* Write to TIMx CCMR1 register */
;;;1327     TIMx->CCMR1 = tmpccmr1;
0009b6  8302              STRH     r2,[r0,#0x18]
;;;1328   }
0009b8  4770              BX       lr
;;;1329   
                          ENDP

                  TIM_ForcedOC2Config PROC
;;;1338     */
;;;1339   void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
0009ba  2200              MOVS     r2,#0
;;;1340   {
;;;1341     uint16_t tmpccmr1 = 0;
;;;1342     /* Check the parameters */
;;;1343     assert_param(IS_TIM_LIST6_PERIPH(TIMx));
;;;1344     assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
;;;1345     tmpccmr1 = TIMx->CCMR1;
0009bc  8b02              LDRH     r2,[r0,#0x18]
;;;1346     /* Reset the OC2M Bits */
;;;1347     tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);
0009be  f64873ff          MOV      r3,#0x8fff
0009c2  401a              ANDS     r2,r2,r3
;;;1348     /* Configure The Forced output Mode */
;;;1349     tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
0009c4  060b              LSLS     r3,r1,#24
0009c6  ea424213          ORR      r2,r2,r3,LSR #16
;;;1350     /* Write to TIMx CCMR1 register */
;;;1351     TIMx->CCMR1 = tmpccmr1;
0009ca  8302              STRH     r2,[r0,#0x18]
;;;1352   }
0009cc  4770              BX       lr
;;;1353   
                          ENDP

                  TIM_ForcedOC3Config PROC
;;;1362     */
;;;1363   void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
0009ce  2200              MOVS     r2,#0
;;;1364   {
;;;1365     uint16_t tmpccmr2 = 0;
;;;1366     /* Check the parameters */
;;;1367     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1368     assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
;;;1369     tmpccmr2 = TIMx->CCMR2;
0009d0  8b82              LDRH     r2,[r0,#0x1c]
;;;1370     /* Reset the OC1M Bits */
;;;1371     tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);
0009d2  f64f738f          MOV      r3,#0xff8f
0009d6  401a              ANDS     r2,r2,r3
;;;1372     /* Configure The Forced output Mode */
;;;1373     tmpccmr2 |= TIM_ForcedAction;
0009d8  430a              ORRS     r2,r2,r1
;;;1374     /* Write to TIMx CCMR2 register */
;;;1375     TIMx->CCMR2 = tmpccmr2;
0009da  8382              STRH     r2,[r0,#0x1c]
;;;1376   }
0009dc  4770              BX       lr
;;;1377   
                          ENDP

                  TIM_ForcedOC4Config PROC
;;;1386     */
;;;1387   void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
0009de  2200              MOVS     r2,#0
;;;1388   {
;;;1389     uint16_t tmpccmr2 = 0;
;;;1390     /* Check the parameters */
;;;1391     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1392     assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
;;;1393     tmpccmr2 = TIMx->CCMR2;
0009e0  8b82              LDRH     r2,[r0,#0x1c]
;;;1394     /* Reset the OC2M Bits */
;;;1395     tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);
0009e2  f64873ff          MOV      r3,#0x8fff
0009e6  401a              ANDS     r2,r2,r3
;;;1396     /* Configure The Forced output Mode */
;;;1397     tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
0009e8  060b              LSLS     r3,r1,#24
0009ea  ea424213          ORR      r2,r2,r3,LSR #16
;;;1398     /* Write to TIMx CCMR2 register */
;;;1399     TIMx->CCMR2 = tmpccmr2;
0009ee  8382              STRH     r2,[r0,#0x1c]
;;;1400   }
0009f0  4770              BX       lr
;;;1401   
                          ENDP

                  TIM_ARRPreloadConfig PROC
;;;1408     */
;;;1409   void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
0009f2  b121              CBZ      r1,|L1.2558|
;;;1410   {
;;;1411     /* Check the parameters */
;;;1412     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;1413     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1414     if (NewState != DISABLE)
;;;1415     {
;;;1416       /* Set the ARR Preload Bit */
;;;1417       TIMx->CR1 |= TIM_CR1_ARPE;
0009f4  8802              LDRH     r2,[r0,#0]
0009f6  f0420280          ORR      r2,r2,#0x80
0009fa  8002              STRH     r2,[r0,#0]
0009fc  e004              B        |L1.2568|
                  |L1.2558|
;;;1418     }
;;;1419     else
;;;1420     {
;;;1421       /* Reset the ARR Preload Bit */
;;;1422       TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);
0009fe  8802              LDRH     r2,[r0,#0]
000a00  f64f737f          MOV      r3,#0xff7f
000a04  401a              ANDS     r2,r2,r3
000a06  8002              STRH     r2,[r0,#0]
                  |L1.2568|
;;;1423     }
;;;1424   }
000a08  4770              BX       lr
;;;1425   
                          ENDP

                  TIM_SelectCOM PROC
;;;1432     */
;;;1433   void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
000a0a  b121              CBZ      r1,|L1.2582|
;;;1434   {
;;;1435     /* Check the parameters */
;;;1436     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;1437     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1438     if (NewState != DISABLE)
;;;1439     {
;;;1440       /* Set the COM Bit */
;;;1441       TIMx->CR2 |= TIM_CR2_CCUS;
000a0c  8882              LDRH     r2,[r0,#4]
000a0e  f0420204          ORR      r2,r2,#4
000a12  8082              STRH     r2,[r0,#4]
000a14  e004              B        |L1.2592|
                  |L1.2582|
;;;1442     }
;;;1443     else
;;;1444     {
;;;1445       /* Reset the COM Bit */
;;;1446       TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS);
000a16  8882              LDRH     r2,[r0,#4]
000a18  f64f73fb          MOV      r3,#0xfffb
000a1c  401a              ANDS     r2,r2,r3
000a1e  8082              STRH     r2,[r0,#4]
                  |L1.2592|
;;;1447     }
;;;1448   }
000a20  4770              BX       lr
;;;1449   
                          ENDP

                  TIM_SelectCCDMA PROC
;;;1457     */
;;;1458   void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
000a22  b121              CBZ      r1,|L1.2606|
;;;1459   {
;;;1460     /* Check the parameters */
;;;1461     assert_param(IS_TIM_LIST4_PERIPH(TIMx));
;;;1462     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1463     if (NewState != DISABLE)
;;;1464     {
;;;1465       /* Set the CCDS Bit */
;;;1466       TIMx->CR2 |= TIM_CR2_CCDS;
000a24  8882              LDRH     r2,[r0,#4]
000a26  f0420208          ORR      r2,r2,#8
000a2a  8082              STRH     r2,[r0,#4]
000a2c  e004              B        |L1.2616|
                  |L1.2606|
;;;1467     }
;;;1468     else
;;;1469     {
;;;1470       /* Reset the CCDS Bit */
;;;1471       TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);
000a2e  8882              LDRH     r2,[r0,#4]
000a30  f64f73f7          MOV      r3,#0xfff7
000a34  401a              ANDS     r2,r2,r3
000a36  8082              STRH     r2,[r0,#4]
                  |L1.2616|
;;;1472     }
;;;1473   }
000a38  4770              BX       lr
;;;1474   
                          ENDP

                  TIM_CCPreloadControl PROC
;;;1482     */
;;;1483   void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
000a3a  b121              CBZ      r1,|L1.2630|
;;;1484   { 
;;;1485     /* Check the parameters */
;;;1486     assert_param(IS_TIM_LIST5_PERIPH(TIMx));
;;;1487     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1488     if (NewState != DISABLE)
;;;1489     {
;;;1490       /* Set the CCPC Bit */
;;;1491       TIMx->CR2 |= TIM_CR2_CCPC;
000a3c  8882              LDRH     r2,[r0,#4]
000a3e  f0420201          ORR      r2,r2,#1
000a42  8082              STRH     r2,[r0,#4]
000a44  e004              B        |L1.2640|
                  |L1.2630|
;;;1492     }
;;;1493     else
;;;1494     {
;;;1495       /* Reset the CCPC Bit */
;;;1496       TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC);
000a46  8882              LDRH     r2,[r0,#4]
000a48  f64f73fe          MOV      r3,#0xfffe
000a4c  401a              ANDS     r2,r2,r3
000a4e  8082              STRH     r2,[r0,#4]
                  |L1.2640|
;;;1497     }
;;;1498   }
000a50  4770              BX       lr
;;;1499   
                          ENDP

                  TIM_OC1PreloadConfig PROC
;;;1508     */
;;;1509   void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
000a52  2200              MOVS     r2,#0
;;;1510   {
;;;1511     uint16_t tmpccmr1 = 0;
;;;1512     /* Check the parameters */
;;;1513     assert_param(IS_TIM_LIST8_PERIPH(TIMx));
;;;1514     assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
;;;1515     tmpccmr1 = TIMx->CCMR1;
000a54  8b02              LDRH     r2,[r0,#0x18]
;;;1516     /* Reset the OC1PE Bit */
;;;1517     tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);
000a56  f64f73f7          MOV      r3,#0xfff7
000a5a  401a              ANDS     r2,r2,r3
;;;1518     /* Enable or Disable the Output Compare Preload feature */
;;;1519     tmpccmr1 |= TIM_OCPreload;
000a5c  430a              ORRS     r2,r2,r1
;;;1520     /* Write to TIMx CCMR1 register */
;;;1521     TIMx->CCMR1 = tmpccmr1;
000a5e  8302              STRH     r2,[r0,#0x18]
;;;1522   }
000a60  4770              BX       lr
;;;1523   
                          ENDP

                  TIM_OC2PreloadConfig PROC
;;;1533     */
;;;1534   void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
000a62  2200              MOVS     r2,#0
;;;1535   {
;;;1536     uint16_t tmpccmr1 = 0;
;;;1537     /* Check the parameters */
;;;1538     assert_param(IS_TIM_LIST6_PERIPH(TIMx));
;;;1539     assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
;;;1540     tmpccmr1 = TIMx->CCMR1;
000a64  8b02              LDRH     r2,[r0,#0x18]
;;;1541     /* Reset the OC2PE Bit */
;;;1542     tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);
000a66  f24f73ff          MOV      r3,#0xf7ff
000a6a  401a              ANDS     r2,r2,r3
;;;1543     /* Enable or Disable the Output Compare Preload feature */
;;;1544     tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
000a6c  060b              LSLS     r3,r1,#24
000a6e  ea424213          ORR      r2,r2,r3,LSR #16
;;;1545     /* Write to TIMx CCMR1 register */
;;;1546     TIMx->CCMR1 = tmpccmr1;
000a72  8302              STRH     r2,[r0,#0x18]
;;;1547   }
000a74  4770              BX       lr
;;;1548   
                          ENDP

                  TIM_OC3PreloadConfig PROC
;;;1557     */
;;;1558   void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
000a76  2200              MOVS     r2,#0
;;;1559   {
;;;1560     uint16_t tmpccmr2 = 0;
;;;1561     /* Check the parameters */
;;;1562     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1563     assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
;;;1564     tmpccmr2 = TIMx->CCMR2;
000a78  8b82              LDRH     r2,[r0,#0x1c]
;;;1565     /* Reset the OC3PE Bit */
;;;1566     tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
000a7a  f64f73f7          MOV      r3,#0xfff7
000a7e  401a              ANDS     r2,r2,r3
;;;1567     /* Enable or Disable the Output Compare Preload feature */
;;;1568     tmpccmr2 |= TIM_OCPreload;
000a80  430a              ORRS     r2,r2,r1
;;;1569     /* Write to TIMx CCMR2 register */
;;;1570     TIMx->CCMR2 = tmpccmr2;
000a82  8382              STRH     r2,[r0,#0x1c]
;;;1571   }
000a84  4770              BX       lr
;;;1572   
                          ENDP

                  TIM_OC4PreloadConfig PROC
;;;1581     */
;;;1582   void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
000a86  2200              MOVS     r2,#0
;;;1583   {
;;;1584     uint16_t tmpccmr2 = 0;
;;;1585     /* Check the parameters */
;;;1586     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1587     assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
;;;1588     tmpccmr2 = TIMx->CCMR2;
000a88  8b82              LDRH     r2,[r0,#0x1c]
;;;1589     /* Reset the OC4PE Bit */
;;;1590     tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);
000a8a  f24f73ff          MOV      r3,#0xf7ff
000a8e  401a              ANDS     r2,r2,r3
;;;1591     /* Enable or Disable the Output Compare Preload feature */
;;;1592     tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
000a90  060b              LSLS     r3,r1,#24
000a92  ea424213          ORR      r2,r2,r3,LSR #16
;;;1593     /* Write to TIMx CCMR2 register */
;;;1594     TIMx->CCMR2 = tmpccmr2;
000a96  8382              STRH     r2,[r0,#0x1c]
;;;1595   }
000a98  4770              BX       lr
;;;1596   
                          ENDP

                  TIM_OC1FastConfig PROC
;;;1605     */
;;;1606   void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
000a9a  2200              MOVS     r2,#0
;;;1607   {
;;;1608     uint16_t tmpccmr1 = 0;
;;;1609     /* Check the parameters */
;;;1610     assert_param(IS_TIM_LIST8_PERIPH(TIMx));
;;;1611     assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
;;;1612     /* Get the TIMx CCMR1 register value */
;;;1613     tmpccmr1 = TIMx->CCMR1;
000a9c  8b02              LDRH     r2,[r0,#0x18]
;;;1614     /* Reset the OC1FE Bit */
;;;1615     tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);
000a9e  f64f73fb          MOV      r3,#0xfffb
000aa2  401a              ANDS     r2,r2,r3
;;;1616     /* Enable or Disable the Output Compare Fast Bit */
;;;1617     tmpccmr1 |= TIM_OCFast;
000aa4  430a              ORRS     r2,r2,r1
;;;1618     /* Write to TIMx CCMR1 */
;;;1619     TIMx->CCMR1 = tmpccmr1;
000aa6  8302              STRH     r2,[r0,#0x18]
;;;1620   }
000aa8  4770              BX       lr
;;;1621   
                          ENDP

                  TIM_OC2FastConfig PROC
;;;1631     */
;;;1632   void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
000aaa  2200              MOVS     r2,#0
;;;1633   {
;;;1634     uint16_t tmpccmr1 = 0;
;;;1635     /* Check the parameters */
;;;1636     assert_param(IS_TIM_LIST6_PERIPH(TIMx));
;;;1637     assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
;;;1638     /* Get the TIMx CCMR1 register value */
;;;1639     tmpccmr1 = TIMx->CCMR1;
000aac  8b02              LDRH     r2,[r0,#0x18]
;;;1640     /* Reset the OC2FE Bit */
;;;1641     tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);
000aae  f64f33ff          MOV      r3,#0xfbff
000ab2  401a              ANDS     r2,r2,r3
;;;1642     /* Enable or Disable the Output Compare Fast Bit */
;;;1643     tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
000ab4  060b              LSLS     r3,r1,#24
000ab6  ea424213          ORR      r2,r2,r3,LSR #16
;;;1644     /* Write to TIMx CCMR1 */
;;;1645     TIMx->CCMR1 = tmpccmr1;
000aba  8302              STRH     r2,[r0,#0x18]
;;;1646   }
000abc  4770              BX       lr
;;;1647   
                          ENDP

                  TIM_OC3FastConfig PROC
;;;1656     */
;;;1657   void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
000abe  2200              MOVS     r2,#0
;;;1658   {
;;;1659     uint16_t tmpccmr2 = 0;
;;;1660     /* Check the parameters */
;;;1661     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1662     assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
;;;1663     /* Get the TIMx CCMR2 register value */
;;;1664     tmpccmr2 = TIMx->CCMR2;
000ac0  8b82              LDRH     r2,[r0,#0x1c]
;;;1665     /* Reset the OC3FE Bit */
;;;1666     tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);
000ac2  f64f73fb          MOV      r3,#0xfffb
000ac6  401a              ANDS     r2,r2,r3
;;;1667     /* Enable or Disable the Output Compare Fast Bit */
;;;1668     tmpccmr2 |= TIM_OCFast;
000ac8  430a              ORRS     r2,r2,r1
;;;1669     /* Write to TIMx CCMR2 */
;;;1670     TIMx->CCMR2 = tmpccmr2;
000aca  8382              STRH     r2,[r0,#0x1c]
;;;1671   }
000acc  4770              BX       lr
;;;1672   
                          ENDP

                  TIM_OC4FastConfig PROC
;;;1681     */
;;;1682   void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
000ace  2200              MOVS     r2,#0
;;;1683   {
;;;1684     uint16_t tmpccmr2 = 0;
;;;1685     /* Check the parameters */
;;;1686     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1687     assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
;;;1688     /* Get the TIMx CCMR2 register value */
;;;1689     tmpccmr2 = TIMx->CCMR2;
000ad0  8b82              LDRH     r2,[r0,#0x1c]
;;;1690     /* Reset the OC4FE Bit */
;;;1691     tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);
000ad2  f64f33ff          MOV      r3,#0xfbff
000ad6  401a              ANDS     r2,r2,r3
;;;1692     /* Enable or Disable the Output Compare Fast Bit */
;;;1693     tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
000ad8  060b              LSLS     r3,r1,#24
000ada  ea424213          ORR      r2,r2,r3,LSR #16
;;;1694     /* Write to TIMx CCMR2 */
;;;1695     TIMx->CCMR2 = tmpccmr2;
000ade  8382              STRH     r2,[r0,#0x1c]
;;;1696   }
000ae0  4770              BX       lr
;;;1697   
                          ENDP

                  TIM_ClearOC1Ref PROC
;;;1706     */
;;;1707   void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
000ae2  2200              MOVS     r2,#0
;;;1708   {
;;;1709     uint16_t tmpccmr1 = 0;
;;;1710     /* Check the parameters */
;;;1711     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1712     assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
;;;1713   
;;;1714     tmpccmr1 = TIMx->CCMR1;
000ae4  8b02              LDRH     r2,[r0,#0x18]
;;;1715   
;;;1716     /* Reset the OC1CE Bit */
;;;1717     tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);
000ae6  f64f737f          MOV      r3,#0xff7f
000aea  401a              ANDS     r2,r2,r3
;;;1718     /* Enable or Disable the Output Compare Clear Bit */
;;;1719     tmpccmr1 |= TIM_OCClear;
000aec  430a              ORRS     r2,r2,r1
;;;1720     /* Write to TIMx CCMR1 register */
;;;1721     TIMx->CCMR1 = tmpccmr1;
000aee  8302              STRH     r2,[r0,#0x18]
;;;1722   }
000af0  4770              BX       lr
;;;1723   
                          ENDP

                  TIM_ClearOC2Ref PROC
;;;1732     */
;;;1733   void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
000af2  2200              MOVS     r2,#0
;;;1734   {
;;;1735     uint16_t tmpccmr1 = 0;
;;;1736     /* Check the parameters */
;;;1737     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1738     assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
;;;1739     tmpccmr1 = TIMx->CCMR1;
000af4  8b02              LDRH     r2,[r0,#0x18]
;;;1740     /* Reset the OC2CE Bit */
;;;1741     tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
000af6  f3c2020e          UBFX     r2,r2,#0,#15
;;;1742     /* Enable or Disable the Output Compare Clear Bit */
;;;1743     tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
000afa  060b              LSLS     r3,r1,#24
000afc  ea424213          ORR      r2,r2,r3,LSR #16
;;;1744     /* Write to TIMx CCMR1 register */
;;;1745     TIMx->CCMR1 = tmpccmr1;
000b00  8302              STRH     r2,[r0,#0x18]
;;;1746   }
000b02  4770              BX       lr
;;;1747   
                          ENDP

                  TIM_ClearOC3Ref PROC
;;;1756     */
;;;1757   void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
000b04  2200              MOVS     r2,#0
;;;1758   {
;;;1759     uint16_t tmpccmr2 = 0;
;;;1760     /* Check the parameters */
;;;1761     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1762     assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
;;;1763     tmpccmr2 = TIMx->CCMR2;
000b06  8b82              LDRH     r2,[r0,#0x1c]
;;;1764     /* Reset the OC3CE Bit */
;;;1765     tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);
000b08  f64f737f          MOV      r3,#0xff7f
000b0c  401a              ANDS     r2,r2,r3
;;;1766     /* Enable or Disable the Output Compare Clear Bit */
;;;1767     tmpccmr2 |= TIM_OCClear;
000b0e  430a              ORRS     r2,r2,r1
;;;1768     /* Write to TIMx CCMR2 register */
;;;1769     TIMx->CCMR2 = tmpccmr2;
000b10  8382              STRH     r2,[r0,#0x1c]
;;;1770   }
000b12  4770              BX       lr
;;;1771   
                          ENDP

                  TIM_ClearOC4Ref PROC
;;;1780     */
;;;1781   void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
000b14  2200              MOVS     r2,#0
;;;1782   {
;;;1783     uint16_t tmpccmr2 = 0;
;;;1784     /* Check the parameters */
;;;1785     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1786     assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
;;;1787     tmpccmr2 = TIMx->CCMR2;
000b16  8b82              LDRH     r2,[r0,#0x1c]
;;;1788     /* Reset the OC4CE Bit */
;;;1789     tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);
000b18  f3c2020e          UBFX     r2,r2,#0,#15
;;;1790     /* Enable or Disable the Output Compare Clear Bit */
;;;1791     tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
000b1c  060b              LSLS     r3,r1,#24
000b1e  ea424213          ORR      r2,r2,r3,LSR #16
;;;1792     /* Write to TIMx CCMR2 register */
;;;1793     TIMx->CCMR2 = tmpccmr2;
000b22  8382              STRH     r2,[r0,#0x1c]
;;;1794   }
000b24  4770              BX       lr
;;;1795   
                          ENDP

                  TIM_OC1PolarityConfig PROC
;;;1804     */
;;;1805   void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
000b26  2200              MOVS     r2,#0
;;;1806   {
;;;1807     uint16_t tmpccer = 0;
;;;1808     /* Check the parameters */
;;;1809     assert_param(IS_TIM_LIST8_PERIPH(TIMx));
;;;1810     assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
;;;1811     tmpccer = TIMx->CCER;
000b28  8c02              LDRH     r2,[r0,#0x20]
;;;1812     /* Set or Reset the CC1P Bit */
;;;1813     tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);
000b2a  f64f73fd          MOV      r3,#0xfffd
000b2e  401a              ANDS     r2,r2,r3
;;;1814     tmpccer |= TIM_OCPolarity;
000b30  430a              ORRS     r2,r2,r1
;;;1815     /* Write to TIMx CCER register */
;;;1816     TIMx->CCER = tmpccer;
000b32  8402              STRH     r2,[r0,#0x20]
;;;1817   }
000b34  4770              BX       lr
;;;1818   
                          ENDP

                  TIM_OC1NPolarityConfig PROC
;;;1827     */
;;;1828   void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
000b36  2200              MOVS     r2,#0
;;;1829   {
;;;1830     uint16_t tmpccer = 0;
;;;1831     /* Check the parameters */
;;;1832     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;1833     assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
;;;1834      
;;;1835     tmpccer = TIMx->CCER;
000b38  8c02              LDRH     r2,[r0,#0x20]
;;;1836     /* Set or Reset the CC1NP Bit */
;;;1837     tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP);
000b3a  f64f73f7          MOV      r3,#0xfff7
000b3e  401a              ANDS     r2,r2,r3
;;;1838     tmpccer |= TIM_OCNPolarity;
000b40  430a              ORRS     r2,r2,r1
;;;1839     /* Write to TIMx CCER register */
;;;1840     TIMx->CCER = tmpccer;
000b42  8402              STRH     r2,[r0,#0x20]
;;;1841   }
000b44  4770              BX       lr
;;;1842   
                          ENDP

                  TIM_OC2PolarityConfig PROC
;;;1851     */
;;;1852   void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
000b46  2200              MOVS     r2,#0
;;;1853   {
;;;1854     uint16_t tmpccer = 0;
;;;1855     /* Check the parameters */
;;;1856     assert_param(IS_TIM_LIST6_PERIPH(TIMx));
;;;1857     assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
;;;1858     tmpccer = TIMx->CCER;
000b48  8c02              LDRH     r2,[r0,#0x20]
;;;1859     /* Set or Reset the CC2P Bit */
;;;1860     tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);
000b4a  f64f73df          MOV      r3,#0xffdf
000b4e  401a              ANDS     r2,r2,r3
;;;1861     tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
000b50  050b              LSLS     r3,r1,#20
000b52  ea424213          ORR      r2,r2,r3,LSR #16
;;;1862     /* Write to TIMx CCER register */
;;;1863     TIMx->CCER = tmpccer;
000b56  8402              STRH     r2,[r0,#0x20]
;;;1864   }
000b58  4770              BX       lr
;;;1865   
                          ENDP

                  TIM_OC2NPolarityConfig PROC
;;;1874     */
;;;1875   void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
000b5a  2200              MOVS     r2,#0
;;;1876   {
;;;1877     uint16_t tmpccer = 0;
;;;1878     /* Check the parameters */
;;;1879     assert_param(IS_TIM_LIST1_PERIPH(TIMx));
;;;1880     assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
;;;1881     
;;;1882     tmpccer = TIMx->CCER;
000b5c  8c02              LDRH     r2,[r0,#0x20]
;;;1883     /* Set or Reset the CC2NP Bit */
;;;1884     tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP);
000b5e  f64f737f          MOV      r3,#0xff7f
000b62  401a              ANDS     r2,r2,r3
;;;1885     tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
000b64  050b              LSLS     r3,r1,#20
000b66  ea424213          ORR      r2,r2,r3,LSR #16
;;;1886     /* Write to TIMx CCER register */
;;;1887     TIMx->CCER = tmpccer;
000b6a  8402              STRH     r2,[r0,#0x20]
;;;1888   }
000b6c  4770              BX       lr
;;;1889   
                          ENDP

                  TIM_OC3PolarityConfig PROC
;;;1898     */
;;;1899   void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
000b6e  2200              MOVS     r2,#0
;;;1900   {
;;;1901     uint16_t tmpccer = 0;
;;;1902     /* Check the parameters */
;;;1903     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1904     assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
;;;1905     tmpccer = TIMx->CCER;
000b70  8c02              LDRH     r2,[r0,#0x20]
;;;1906     /* Set or Reset the CC3P Bit */
;;;1907     tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);
000b72  f64f53ff          MOV      r3,#0xfdff
000b76  401a              ANDS     r2,r2,r3
;;;1908     tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
000b78  060b              LSLS     r3,r1,#24
000b7a  ea424213          ORR      r2,r2,r3,LSR #16
;;;1909     /* Write to TIMx CCER register */
;;;1910     TIMx->CCER = tmpccer;
000b7e  8402              STRH     r2,[r0,#0x20]
;;;1911   }
000b80  4770              BX       lr
;;;1912   
                          ENDP

                  TIM_OC3NPolarityConfig PROC
;;;1921     */
;;;1922   void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
000b82  2200              MOVS     r2,#0
;;;1923   {
;;;1924     uint16_t tmpccer = 0;
;;;1925    
;;;1926     /* Check the parameters */
;;;1927     assert_param(IS_TIM_LIST1_PERIPH(TIMx));
;;;1928     assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
;;;1929       
;;;1930     tmpccer = TIMx->CCER;
000b84  8c02              LDRH     r2,[r0,#0x20]
;;;1931     /* Set or Reset the CC3NP Bit */
;;;1932     tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP);
000b86  f24f73ff          MOV      r3,#0xf7ff
000b8a  401a              ANDS     r2,r2,r3
;;;1933     tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
000b8c  060b              LSLS     r3,r1,#24
000b8e  ea424213          ORR      r2,r2,r3,LSR #16
;;;1934     /* Write to TIMx CCER register */
;;;1935     TIMx->CCER = tmpccer;
000b92  8402              STRH     r2,[r0,#0x20]
;;;1936   }
000b94  4770              BX       lr
;;;1937   
                          ENDP

                  TIM_OC4PolarityConfig PROC
;;;1946     */
;;;1947   void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
000b96  2200              MOVS     r2,#0
;;;1948   {
;;;1949     uint16_t tmpccer = 0;
;;;1950     /* Check the parameters */
;;;1951     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;1952     assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
;;;1953     tmpccer = TIMx->CCER;
000b98  8c02              LDRH     r2,[r0,#0x20]
;;;1954     /* Set or Reset the CC4P Bit */
;;;1955     tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);
000b9a  f64d73ff          MOV      r3,#0xdfff
000b9e  401a              ANDS     r2,r2,r3
;;;1956     tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
000ba0  070b              LSLS     r3,r1,#28
000ba2  ea424213          ORR      r2,r2,r3,LSR #16
;;;1957     /* Write to TIMx CCER register */
;;;1958     TIMx->CCER = tmpccer;
000ba6  8402              STRH     r2,[r0,#0x20]
;;;1959   }
000ba8  4770              BX       lr
;;;1960   
                          ENDP

                  TIM_CCxCmd PROC
;;;1973     */
;;;1974   void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
000baa  b530              PUSH     {r4,r5,lr}
;;;1975   {
;;;1976     uint16_t tmp = 0;
000bac  2300              MOVS     r3,#0
;;;1977   
;;;1978     /* Check the parameters */
;;;1979     assert_param(IS_TIM_LIST8_PERIPH(TIMx));
;;;1980     assert_param(IS_TIM_CHANNEL(TIM_Channel));
;;;1981     assert_param(IS_TIM_CCX(TIM_CCx));
;;;1982   
;;;1983     tmp = CCER_CCE_Set << TIM_Channel;
000bae  2401              MOVS     r4,#1
000bb0  408c              LSLS     r4,r4,r1
000bb2  b2a3              UXTH     r3,r4
;;;1984   
;;;1985     /* Reset the CCxE Bit */
;;;1986     TIMx->CCER &= (uint16_t)~ tmp;
000bb4  8c04              LDRH     r4,[r0,#0x20]
000bb6  43dd              MVNS     r5,r3
000bb8  b2ad              UXTH     r5,r5
000bba  402c              ANDS     r4,r4,r5
000bbc  8404              STRH     r4,[r0,#0x20]
;;;1987   
;;;1988     /* Set or reset the CCxE Bit */ 
;;;1989     TIMx->CCER |=  (uint16_t)(TIM_CCx << TIM_Channel);
000bbe  8c04              LDRH     r4,[r0,#0x20]
000bc0  fa02f501          LSL      r5,r2,r1
000bc4  b2ad              UXTH     r5,r5
000bc6  432c              ORRS     r4,r4,r5
000bc8  8404              STRH     r4,[r0,#0x20]
;;;1990   }
000bca  bd30              POP      {r4,r5,pc}
;;;1991   
                          ENDP

                  TIM_CCxNCmd PROC
;;;2003     */
;;;2004   void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
000bcc  b530              PUSH     {r4,r5,lr}
;;;2005   {
;;;2006     uint16_t tmp = 0;
000bce  2300              MOVS     r3,#0
;;;2007   
;;;2008     /* Check the parameters */
;;;2009     assert_param(IS_TIM_LIST2_PERIPH(TIMx));
;;;2010     assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
;;;2011     assert_param(IS_TIM_CCXN(TIM_CCxN));
;;;2012   
;;;2013     tmp = CCER_CCNE_Set << TIM_Channel;
000bd0  2404              MOVS     r4,#4
000bd2  408c              LSLS     r4,r4,r1
000bd4  b2a3              UXTH     r3,r4
;;;2014   
;;;2015     /* Reset the CCxNE Bit */
;;;2016     TIMx->CCER &= (uint16_t) ~tmp;
000bd6  8c04              LDRH     r4,[r0,#0x20]
000bd8  43dd              MVNS     r5,r3
000bda  b2ad              UXTH     r5,r5
000bdc  402c              ANDS     r4,r4,r5
000bde  8404              STRH     r4,[r0,#0x20]
;;;2017   
;;;2018     /* Set or reset the CCxNE Bit */ 
;;;2019     TIMx->CCER |=  (uint16_t)(TIM_CCxN << TIM_Channel);
000be0  8c04              LDRH     r4,[r0,#0x20]
000be2  fa02f501          LSL      r5,r2,r1
000be6  b2ad              UXTH     r5,r5
000be8  432c              ORRS     r4,r4,r5
000bea  8404              STRH     r4,[r0,#0x20]
;;;2020   }
000bec  bd30              POP      {r4,r5,pc}
;;;2021   
                          ENDP

                  TIM_SelectOCxM PROC
;;;2044     */
;;;2045   void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
000bee  b570              PUSH     {r4-r6,lr}
;;;2046   {
;;;2047     uint32_t tmp = 0;
000bf0  2300              MOVS     r3,#0
;;;2048     uint16_t tmp1 = 0;
000bf2  2400              MOVS     r4,#0
;;;2049   
;;;2050     /* Check the parameters */
;;;2051     assert_param(IS_TIM_LIST8_PERIPH(TIMx));
;;;2052     assert_param(IS_TIM_CHANNEL(TIM_Channel));
;;;2053     assert_param(IS_TIM_OCM(TIM_OCMode));
;;;2054   
;;;2055     tmp = (uint32_t) TIMx;
000bf4  4603              MOV      r3,r0
;;;2056     tmp += CCMR_Offset;
000bf6  4618              MOV      r0,r3
000bf8  3318              ADDS     r3,r3,#0x18
;;;2057   
;;;2058     tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel;
000bfa  2501              MOVS     r5,#1
000bfc  408d              LSLS     r5,r5,r1
000bfe  b2ac              UXTH     r4,r5
;;;2059   
;;;2060     /* Disable the Channel: Reset the CCxE Bit */
;;;2061     TIMx->CCER &= (uint16_t) ~tmp1;
000c00  8c05              LDRH     r5,[r0,#0x20]
000c02  43e6              MVNS     r6,r4
000c04  b2b6              UXTH     r6,r6
000c06  4035              ANDS     r5,r5,r6
000c08  8405              STRH     r5,[r0,#0x20]
;;;2062   
;;;2063     if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
000c0a  b109              CBZ      r1,|L1.3088|
000c0c  2908              CMP      r1,#8
000c0e  d109              BNE      |L1.3108|
                  |L1.3088|
;;;2064     {
;;;2065       tmp += (TIM_Channel>>1);
000c10  eb030361          ADD      r3,r3,r1,ASR #1
;;;2066   
;;;2067       /* Reset the OCxM bits in the CCMRx register */
;;;2068       *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
000c14  681d              LDR      r5,[r3,#0]
000c16  f0250570          BIC      r5,r5,#0x70
000c1a  601d              STR      r5,[r3,#0]
;;;2069      
;;;2070       /* Configure the OCxM bits in the CCMRx register */
;;;2071       *(__IO uint32_t *) tmp |= TIM_OCMode;
000c1c  681d              LDR      r5,[r3,#0]
000c1e  4315              ORRS     r5,r5,r2
000c20  601d              STR      r5,[r3,#0]
000c22  e00c              B        |L1.3134|
                  |L1.3108|
;;;2072     }
;;;2073     else
;;;2074     {
;;;2075       tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
000c24  1f0d              SUBS     r5,r1,#4
000c26  b2ad              UXTH     r5,r5
000c28  eb030365          ADD      r3,r3,r5,ASR #1
;;;2076   
;;;2077       /* Reset the OCxM bits in the CCMRx register */
;;;2078       *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
000c2c  681d              LDR      r5,[r3,#0]
000c2e  f42545e0          BIC      r5,r5,#0x7000
000c32  601d              STR      r5,[r3,#0]
;;;2079       
;;;2080       /* Configure the OCxM bits in the CCMRx register */
;;;2081       *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
000c34  681d              LDR      r5,[r3,#0]
000c36  0616              LSLS     r6,r2,#24
000c38  ea454516          ORR      r5,r5,r6,LSR #16
000c3c  601d              STR      r5,[r3,#0]
                  |L1.3134|
;;;2082     }
;;;2083   }
000c3e  bd70              POP      {r4-r6,pc}
;;;2084   
                          ENDP

                  TIM_UpdateDisableConfig PROC
;;;2091     */
;;;2092   void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
000c40  b121              CBZ      r1,|L1.3148|
;;;2093   {
;;;2094     /* Check the parameters */
;;;2095     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2096     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;2097     if (NewState != DISABLE)
;;;2098     {
;;;2099       /* Set the Update Disable Bit */
;;;2100       TIMx->CR1 |= TIM_CR1_UDIS;
000c42  8802              LDRH     r2,[r0,#0]
000c44  f0420202          ORR      r2,r2,#2
000c48  8002              STRH     r2,[r0,#0]
000c4a  e004              B        |L1.3158|
                  |L1.3148|
;;;2101     }
;;;2102     else
;;;2103     {
;;;2104       /* Reset the Update Disable Bit */
;;;2105       TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);
000c4c  8802              LDRH     r2,[r0,#0]
000c4e  f64f73fd          MOV      r3,#0xfffd
000c52  401a              ANDS     r2,r2,r3
000c54  8002              STRH     r2,[r0,#0]
                  |L1.3158|
;;;2106     }
;;;2107   }
000c56  4770              BX       lr
;;;2108   
                          ENDP

                  TIM_UpdateRequestConfig PROC
;;;2119     */
;;;2120   void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
000c58  b121              CBZ      r1,|L1.3172|
;;;2121   {
;;;2122     /* Check the parameters */
;;;2123     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2124     assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
;;;2125     if (TIM_UpdateSource != TIM_UpdateSource_Global)
;;;2126     {
;;;2127       /* Set the URS Bit */
;;;2128       TIMx->CR1 |= TIM_CR1_URS;
000c5a  8802              LDRH     r2,[r0,#0]
000c5c  f0420204          ORR      r2,r2,#4
000c60  8002              STRH     r2,[r0,#0]
000c62  e004              B        |L1.3182|
                  |L1.3172|
;;;2129     }
;;;2130     else
;;;2131     {
;;;2132       /* Reset the URS Bit */
;;;2133       TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);
000c64  8802              LDRH     r2,[r0,#0]
000c66  f64f73fb          MOV      r3,#0xfffb
000c6a  401a              ANDS     r2,r2,r3
000c6c  8002              STRH     r2,[r0,#0]
                  |L1.3182|
;;;2134     }
;;;2135   }
000c6e  4770              BX       lr
;;;2136   
                          ENDP

                  TIM_SelectHallSensor PROC
;;;2143     */
;;;2144   void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
000c70  b121              CBZ      r1,|L1.3196|
;;;2145   {
;;;2146     /* Check the parameters */
;;;2147     assert_param(IS_TIM_LIST6_PERIPH(TIMx));
;;;2148     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;2149     if (NewState != DISABLE)
;;;2150     {
;;;2151       /* Set the TI1S Bit */
;;;2152       TIMx->CR2 |= TIM_CR2_TI1S;
000c72  8882              LDRH     r2,[r0,#4]
000c74  f0420280          ORR      r2,r2,#0x80
000c78  8082              STRH     r2,[r0,#4]
000c7a  e004              B        |L1.3206|
                  |L1.3196|
;;;2153     }
;;;2154     else
;;;2155     {
;;;2156       /* Reset the TI1S Bit */
;;;2157       TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);
000c7c  8882              LDRH     r2,[r0,#4]
000c7e  f64f737f          MOV      r3,#0xff7f
000c82  401a              ANDS     r2,r2,r3
000c84  8082              STRH     r2,[r0,#4]
                  |L1.3206|
;;;2158     }
;;;2159   }
000c86  4770              BX       lr
;;;2160   
                          ENDP

                  TIM_SelectOnePulseMode PROC
;;;2169     */
;;;2170   void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
000c88  8802              LDRH     r2,[r0,#0]
;;;2171   {
;;;2172     /* Check the parameters */
;;;2173     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2174     assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
;;;2175     /* Reset the OPM Bit */
;;;2176     TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);
000c8a  f64f73f7          MOV      r3,#0xfff7
000c8e  401a              ANDS     r2,r2,r3
000c90  8002              STRH     r2,[r0,#0]
;;;2177     /* Configure the OPM Mode */
;;;2178     TIMx->CR1 |= TIM_OPMode;
000c92  8802              LDRH     r2,[r0,#0]
000c94  430a              ORRS     r2,r2,r1
000c96  8002              STRH     r2,[r0,#0]
;;;2179   }
000c98  4770              BX       lr
;;;2180   
                          ENDP

                  TIM_SelectOutputTrigger PROC
;;;2201     */
;;;2202   void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
000c9a  8882              LDRH     r2,[r0,#4]
;;;2203   {
;;;2204     /* Check the parameters */
;;;2205     assert_param(IS_TIM_LIST7_PERIPH(TIMx));
;;;2206     assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
;;;2207     /* Reset the MMS Bits */
;;;2208     TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);
000c9c  f64f738f          MOV      r3,#0xff8f
000ca0  401a              ANDS     r2,r2,r3
000ca2  8082              STRH     r2,[r0,#4]
;;;2209     /* Select the TRGO source */
;;;2210     TIMx->CR2 |=  TIM_TRGOSource;
000ca4  8882              LDRH     r2,[r0,#4]
000ca6  430a              ORRS     r2,r2,r1
000ca8  8082              STRH     r2,[r0,#4]
;;;2211   }
000caa  4770              BX       lr
;;;2212   
                          ENDP

                  TIM_SelectSlaveMode PROC
;;;2224     */
;;;2225   void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
000cac  8902              LDRH     r2,[r0,#8]
;;;2226   {
;;;2227     /* Check the parameters */
;;;2228     assert_param(IS_TIM_LIST6_PERIPH(TIMx));
;;;2229     assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
;;;2230    /* Reset the SMS Bits */
;;;2231     TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);
000cae  f64f73f8          MOV      r3,#0xfff8
000cb2  401a              ANDS     r2,r2,r3
000cb4  8102              STRH     r2,[r0,#8]
;;;2232     /* Select the Slave Mode */
;;;2233     TIMx->SMCR |= TIM_SlaveMode;
000cb6  8902              LDRH     r2,[r0,#8]
000cb8  430a              ORRS     r2,r2,r1
000cba  8102              STRH     r2,[r0,#8]
;;;2234   }
000cbc  4770              BX       lr
;;;2235   
                          ENDP

                  TIM_SelectMasterSlaveMode PROC
;;;2245     */
;;;2246   void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
000cbe  8902              LDRH     r2,[r0,#8]
;;;2247   {
;;;2248     /* Check the parameters */
;;;2249     assert_param(IS_TIM_LIST6_PERIPH(TIMx));
;;;2250     assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
;;;2251     /* Reset the MSM Bit */
;;;2252     TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);
000cc0  f64f737f          MOV      r3,#0xff7f
000cc4  401a              ANDS     r2,r2,r3
000cc6  8102              STRH     r2,[r0,#8]
;;;2253     
;;;2254     /* Set or Reset the MSM Bit */
;;;2255     TIMx->SMCR |= TIM_MasterSlaveMode;
000cc8  8902              LDRH     r2,[r0,#8]
000cca  430a              ORRS     r2,r2,r1
000ccc  8102              STRH     r2,[r0,#8]
;;;2256   }
000cce  4770              BX       lr
;;;2257   
                          ENDP

                  TIM_SetCounter PROC
;;;2263     */
;;;2264   void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter)
000cd0  8481              STRH     r1,[r0,#0x24]
;;;2265   {
;;;2266     /* Check the parameters */
;;;2267     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2268     /* Set the Counter Register value */
;;;2269     TIMx->CNT = Counter;
;;;2270   }
000cd2  4770              BX       lr
;;;2271   
                          ENDP

                  TIM_SetAutoreload PROC
;;;2277     */
;;;2278   void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload)
000cd4  8581              STRH     r1,[r0,#0x2c]
;;;2279   {
;;;2280     /* Check the parameters */
;;;2281     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2282     /* Set the Autoreload Register value */
;;;2283     TIMx->ARR = Autoreload;
;;;2284   }
000cd6  4770              BX       lr
;;;2285   
                          ENDP

                  TIM_SetCompare1 PROC
;;;2291     */
;;;2292   void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1)
000cd8  8681              STRH     r1,[r0,#0x34]
;;;2293   {
;;;2294     /* Check the parameters */
;;;2295     assert_param(IS_TIM_LIST8_PERIPH(TIMx));
;;;2296     /* Set the Capture Compare1 Register value */
;;;2297     TIMx->CCR1 = Compare1;
;;;2298   }
000cda  4770              BX       lr
;;;2299   
                          ENDP

                  TIM_SetCompare2 PROC
;;;2305     */
;;;2306   void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)
000cdc  8701              STRH     r1,[r0,#0x38]
;;;2307   {
;;;2308     /* Check the parameters */
;;;2309     assert_param(IS_TIM_LIST6_PERIPH(TIMx));
;;;2310     /* Set the Capture Compare2 Register value */
;;;2311     TIMx->CCR2 = Compare2;
;;;2312   }
000cde  4770              BX       lr
;;;2313   
                          ENDP

                  TIM_SetCompare3 PROC
;;;2319     */
;;;2320   void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)
000ce0  8781              STRH     r1,[r0,#0x3c]
;;;2321   {
;;;2322     /* Check the parameters */
;;;2323     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;2324     /* Set the Capture Compare3 Register value */
;;;2325     TIMx->CCR3 = Compare3;
;;;2326   }
000ce2  4770              BX       lr
;;;2327   
                          ENDP

                  TIM_SetCompare4 PROC
;;;2333     */
;;;2334   void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)
000ce4  f8a01040          STRH     r1,[r0,#0x40]
;;;2335   {
;;;2336     /* Check the parameters */
;;;2337     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;2338     /* Set the Capture Compare4 Register value */
;;;2339     TIMx->CCR4 = Compare4;
;;;2340   }
000ce8  4770              BX       lr
;;;2341   
                          ENDP

                  TIM_SetClockDivision PROC
;;;2440     */
;;;2441   void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
000cea  8802              LDRH     r2,[r0,#0]
;;;2442   {
;;;2443     /* Check the parameters */
;;;2444     assert_param(IS_TIM_LIST8_PERIPH(TIMx));
;;;2445     assert_param(IS_TIM_CKD_DIV(TIM_CKD));
;;;2446     /* Reset the CKD Bits */
;;;2447     TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);
000cec  f64f43ff          MOV      r3,#0xfcff
000cf0  401a              ANDS     r2,r2,r3
000cf2  8002              STRH     r2,[r0,#0]
;;;2448     /* Set the CKD value */
;;;2449     TIMx->CR1 |= TIM_CKD;
000cf4  8802              LDRH     r2,[r0,#0]
000cf6  430a              ORRS     r2,r2,r1
000cf8  8002              STRH     r2,[r0,#0]
;;;2450   }
000cfa  4770              BX       lr
;;;2451   
                          ENDP

                  TIM_GetCapture1 PROC
;;;2456     */
;;;2457   uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx)
000cfc  4601              MOV      r1,r0
;;;2458   {
;;;2459     /* Check the parameters */
;;;2460     assert_param(IS_TIM_LIST8_PERIPH(TIMx));
;;;2461     /* Get the Capture 1 Register value */
;;;2462     return TIMx->CCR1;
000cfe  8e88              LDRH     r0,[r1,#0x34]
;;;2463   }
000d00  4770              BX       lr
;;;2464   
                          ENDP

                  TIM_GetCapture2 PROC
;;;2469     */
;;;2470   uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx)
000d02  4601              MOV      r1,r0
;;;2471   {
;;;2472     /* Check the parameters */
;;;2473     assert_param(IS_TIM_LIST6_PERIPH(TIMx));
;;;2474     /* Get the Capture 2 Register value */
;;;2475     return TIMx->CCR2;
000d04  8f08              LDRH     r0,[r1,#0x38]
;;;2476   }
000d06  4770              BX       lr
;;;2477   
                          ENDP

                  TIM_GetCapture3 PROC
;;;2482     */
;;;2483   uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx)
000d08  4601              MOV      r1,r0
;;;2484   {
;;;2485     /* Check the parameters */
;;;2486     assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
;;;2487     /* Get the Capture 3 Register value */
;;;2488     return TIMx->CCR3;
000d0a  8f88              LDRH     r0,[r1,#0x3c]
;;;2489   }
000d0c  4770              BX       lr
;;;2490   
                          ENDP

                  TIM_GetCapture4 PROC
;;;2495     */
;;;2496   uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx)
000d0e  4601              MOV      r1,r0
;;;2497   {
;;;2498     /* Check the parameters */
;;;2499     assert_param(IS_TIM_LIST3_PERIPH(TIMx));
;;;2500     /* Get the Capture 4 Register value */
;;;2501     return TIMx->CCR4;
000d10  f8b10040          LDRH     r0,[r1,#0x40]
;;;2502   }
000d14  4770              BX       lr
;;;2503   
                          ENDP

                  TIM_GetCounter PROC
;;;2508     */
;;;2509   uint16_t TIM_GetCounter(TIM_TypeDef* TIMx)
000d16  4601              MOV      r1,r0
;;;2510   {
;;;2511     /* Check the parameters */
;;;2512     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2513     /* Get the Counter Register value */
;;;2514     return TIMx->CNT;
000d18  8c88              LDRH     r0,[r1,#0x24]
;;;2515   }
000d1a  4770              BX       lr
;;;2516   
                          ENDP

                  TIM_GetPrescaler PROC
;;;2521     */
;;;2522   uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
000d1c  4601              MOV      r1,r0
;;;2523   {
;;;2524     /* Check the parameters */
;;;2525     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2526     /* Get the Prescaler Register value */
;;;2527     return TIMx->PSC;
000d1e  8d08              LDRH     r0,[r1,#0x28]
;;;2528   }
000d20  4770              BX       lr
;;;2529   
                          ENDP

                  TIM_GetFlagStatus PROC
;;;2555     */
;;;2556   FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
000d22  4602              MOV      r2,r0
;;;2557   { 
;;;2558     ITStatus bitstatus = RESET;  
000d24  2000              MOVS     r0,#0
;;;2559     /* Check the parameters */
;;;2560     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2561     assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
;;;2562     
;;;2563     if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
000d26  8a13              LDRH     r3,[r2,#0x10]
000d28  420b              TST      r3,r1
000d2a  d001              BEQ      |L1.3376|
;;;2564     {
;;;2565       bitstatus = SET;
000d2c  2001              MOVS     r0,#1
000d2e  e000              B        |L1.3378|
                  |L1.3376|
;;;2566     }
;;;2567     else
;;;2568     {
;;;2569       bitstatus = RESET;
000d30  2000              MOVS     r0,#0
                  |L1.3378|
;;;2570     }
;;;2571     return bitstatus;
;;;2572   }
000d32  4770              BX       lr
;;;2573   
                          ENDP

                  TIM_ClearFlag PROC
;;;2599     */
;;;2600   void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
000d34  43ca              MVNS     r2,r1
;;;2601   {  
;;;2602     /* Check the parameters */
;;;2603     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2604     assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
;;;2605      
;;;2606     /* Clear the flags */
;;;2607     TIMx->SR = (uint16_t)~TIM_FLAG;
000d36  8202              STRH     r2,[r0,#0x10]
;;;2608   }
000d38  4770              BX       lr
;;;2609   
                          ENDP

                  TIM_GetITStatus PROC
;;;2631     */
;;;2632   ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
000d3a  b530              PUSH     {r4,r5,lr}
;;;2633   {
000d3c  4602              MOV      r2,r0
;;;2634     ITStatus bitstatus = RESET;  
000d3e  2000              MOVS     r0,#0
;;;2635     uint16_t itstatus = 0x0, itenable = 0x0;
000d40  2300              MOVS     r3,#0
000d42  2400              MOVS     r4,#0
;;;2636     /* Check the parameters */
;;;2637     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2638     assert_param(IS_TIM_GET_IT(TIM_IT));
;;;2639      
;;;2640     itstatus = TIMx->SR & TIM_IT;
000d44  8a15              LDRH     r5,[r2,#0x10]
000d46  ea050301          AND      r3,r5,r1
;;;2641     
;;;2642     itenable = TIMx->DIER & TIM_IT;
000d4a  8995              LDRH     r5,[r2,#0xc]
000d4c  ea050401          AND      r4,r5,r1
;;;2643     if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
000d50  b113              CBZ      r3,|L1.3416|
000d52  b10c              CBZ      r4,|L1.3416|
;;;2644     {
;;;2645       bitstatus = SET;
000d54  2001              MOVS     r0,#1
000d56  e000              B        |L1.3418|
                  |L1.3416|
;;;2646     }
;;;2647     else
;;;2648     {
;;;2649       bitstatus = RESET;
000d58  2000              MOVS     r0,#0
                  |L1.3418|
;;;2650     }
;;;2651     return bitstatus;
;;;2652   }
000d5a  bd30              POP      {r4,r5,pc}
;;;2653   
                          ENDP

                  TIM_ClearITPendingBit PROC
;;;2675     */
;;;2676   void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
000d5c  43ca              MVNS     r2,r1
;;;2677   {
;;;2678     /* Check the parameters */
;;;2679     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2680     assert_param(IS_TIM_IT(TIM_IT));
;;;2681     /* Clear the IT pending Bit */
;;;2682     TIMx->SR = (uint16_t)~TIM_IT;
000d5e  8202              STRH     r2,[r0,#0x10]
;;;2683   }
000d60  4770              BX       lr
;;;2684   
                          ENDP

