; generated by Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]
; commandline ArmCC [--list --debug -c --asm --interleave -o.\obj\sbus.o --asm_dir=.\list\ --list_dir=.\list\ --depend=.\obj\sbus.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931 -I.\FWlib\inc -I.\user -I.\CM3 -I.\dmp -I.\user\delay -I.\user\sys -I.\user\usart -I.\RTE\_STM32-FD -If:\Users\Administrator\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -If:\Users\Administrator\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=530 -D_RTE_ -DSTM32F10X_MD -D_RTE_ -DUSE_STDPERIPH_DRIVER -DSTM32F10X_MD --omf_browse=.\obj\sbus.crf user\SBUS.c]
                          THUMB

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  UART2_SBUS_init PROC
;;;5      
;;;6      void UART2_SBUS_init(void)
000000  b508              PUSH     {r3,lr}
;;;7      {
;;;8      
;;;9          GPIO_InitTypeDef GPIO_InitStructure;
;;;10         RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); //
000002  2101              MOVS     r1,#1
000004  0448              LSLS     r0,r1,#17
000006  f7fffffe          BL       RCC_APB1PeriphClockCmd
;;;11         RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE); //?? 
00000a  2101              MOVS     r1,#1
00000c  2020              MOVS     r0,#0x20
00000e  f7fffffe          BL       RCC_APB2PeriphClockCmd
;;;12     
;;;13         USART_DeInit(USART2);  //????5  
000012  489d              LDR      r0,|L1.648|
000014  f7fffffe          BL       USART_DeInit
;;;14         //USART5_RX   PD2
;;;15         GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
000018  2004              MOVS     r0,#4
00001a  f8ad0000          STRH     r0,[sp,#0]
;;;16         //GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;//????
;;;17         GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;  
00001e  f88d0003          STRB     r0,[sp,#3]
;;;18     		GPIO_Init(GPIOD, &GPIO_InitStructure);  //PD2  RX5
000022  4669              MOV      r1,sp
000024  4899              LDR      r0,|L1.652|
000026  f7fffffe          BL       GPIO_Init
;;;19     
;;;20         //Usart1 NVIC ??
;;;21     
;;;22     }
00002a  bd08              POP      {r3,pc}
;;;23     
                          ENDP

                  Sbus_Data_Count PROC
;;;24     
;;;25     void Sbus_Data_Count(uint8_t *buf)
00002c  7881              LDRB     r1,[r0,#2]
;;;26     {
;;;27     	CH[ 0] = ((int16_t)buf[ 2] >> 0 | ((int16_t)buf[ 3] << 8 )) & 0x07FF;
00002e  78c2              LDRB     r2,[r0,#3]
000030  ea412102          ORR      r1,r1,r2,LSL #8
000034  f3c1010a          UBFX     r1,r1,#0,#11
000038  4a95              LDR      r2,|L1.656|
00003a  8011              STRH     r1,[r2,#0]
;;;28     	CH[ 1] = ((int16_t)buf[ 3] >> 3 | ((int16_t)buf[ 4] << 5 )) & 0x07FF;
00003c  78c1              LDRB     r1,[r0,#3]
00003e  10c9              ASRS     r1,r1,#3
000040  7902              LDRB     r2,[r0,#4]
000042  ea411142          ORR      r1,r1,r2,LSL #5
000046  f3c1010a          UBFX     r1,r1,#0,#11
00004a  4a91              LDR      r2,|L1.656|
00004c  8051              STRH     r1,[r2,#2]
;;;29     	CH[ 2] = ((int16_t)buf[ 4] >> 6 | ((int16_t)buf[ 5] << 2 )  | (int16_t)buf[ 6] << 10 ) & 0x07FF;
00004e  7901              LDRB     r1,[r0,#4]
000050  1189              ASRS     r1,r1,#6
000052  7942              LDRB     r2,[r0,#5]
000054  ea410182          ORR      r1,r1,r2,LSL #2
000058  7982              LDRB     r2,[r0,#6]
00005a  ea412182          ORR      r1,r1,r2,LSL #10
00005e  f3c1010a          UBFX     r1,r1,#0,#11
000062  4a8b              LDR      r2,|L1.656|
000064  8091              STRH     r1,[r2,#4]
;;;30     	CH[ 3] = ((int16_t)buf[ 6] >> 1 | ((int16_t)buf[ 7] << 7 )) & 0x07FF;
000066  7981              LDRB     r1,[r0,#6]
000068  1049              ASRS     r1,r1,#1
00006a  79c2              LDRB     r2,[r0,#7]
00006c  ea4111c2          ORR      r1,r1,r2,LSL #7
000070  f3c1010a          UBFX     r1,r1,#0,#11
000074  4a86              LDR      r2,|L1.656|
000076  80d1              STRH     r1,[r2,#6]
;;;31     	CH[ 4] = ((int16_t)buf[ 7] >> 4 | ((int16_t)buf[ 8] << 4 )) & 0x07FF;
000078  79c1              LDRB     r1,[r0,#7]
00007a  1109              ASRS     r1,r1,#4
00007c  7a02              LDRB     r2,[r0,#8]
00007e  ea411102          ORR      r1,r1,r2,LSL #4
000082  f3c1010a          UBFX     r1,r1,#0,#11
000086  4a82              LDR      r2,|L1.656|
000088  8111              STRH     r1,[r2,#8]
;;;32     	CH[ 5] = ((int16_t)buf[ 8] >> 7 | ((int16_t)buf[ 9] << 1 )  | (int16_t)buf[10] <<  9 ) & 0x07FF;
00008a  7a01              LDRB     r1,[r0,#8]
00008c  11c9              ASRS     r1,r1,#7
00008e  7a42              LDRB     r2,[r0,#9]
000090  ea410142          ORR      r1,r1,r2,LSL #1
000094  7a82              LDRB     r2,[r0,#0xa]
000096  ea412142          ORR      r1,r1,r2,LSL #9
00009a  f3c1010a          UBFX     r1,r1,#0,#11
00009e  4a7c              LDR      r2,|L1.656|
0000a0  8151              STRH     r1,[r2,#0xa]
;;;33     	CH[ 6] = ((int16_t)buf[10] >> 2 | ((int16_t)buf[11] << 6 )) & 0x07FF;
0000a2  7a81              LDRB     r1,[r0,#0xa]
0000a4  1089              ASRS     r1,r1,#2
0000a6  7ac2              LDRB     r2,[r0,#0xb]
0000a8  ea411182          ORR      r1,r1,r2,LSL #6
0000ac  f3c1010a          UBFX     r1,r1,#0,#11
0000b0  4a77              LDR      r2,|L1.656|
0000b2  8191              STRH     r1,[r2,#0xc]
;;;34     	CH[ 7] = ((int16_t)buf[11] >> 5 | ((int16_t)buf[12] << 3 )) & 0x07FF;
0000b4  7ac1              LDRB     r1,[r0,#0xb]
0000b6  1149              ASRS     r1,r1,#5
0000b8  7b02              LDRB     r2,[r0,#0xc]
0000ba  ea4101c2          ORR      r1,r1,r2,LSL #3
0000be  4a74              LDR      r2,|L1.656|
0000c0  81d1              STRH     r1,[r2,#0xe]
;;;35     	
;;;36     	CH[ 8] = ((int16_t)buf[13] << 0 | ((int16_t)buf[14] << 8 )) & 0x07FF;
0000c2  7b41              LDRB     r1,[r0,#0xd]
0000c4  7b82              LDRB     r2,[r0,#0xe]
0000c6  ea412102          ORR      r1,r1,r2,LSL #8
0000ca  f3c1010a          UBFX     r1,r1,#0,#11
0000ce  4a70              LDR      r2,|L1.656|
0000d0  8211              STRH     r1,[r2,#0x10]
;;;37     	CH[ 9] = ((int16_t)buf[14] >> 3 | ((int16_t)buf[15] << 5 )) & 0x07FF;
0000d2  7b81              LDRB     r1,[r0,#0xe]
0000d4  10c9              ASRS     r1,r1,#3
0000d6  7bc2              LDRB     r2,[r0,#0xf]
0000d8  ea411142          ORR      r1,r1,r2,LSL #5
0000dc  f3c1010a          UBFX     r1,r1,#0,#11
0000e0  4a6b              LDR      r2,|L1.656|
0000e2  8251              STRH     r1,[r2,#0x12]
;;;38     	CH[10] = ((int16_t)buf[15] >> 6 | ((int16_t)buf[16] << 2 )  | (int16_t)buf[17] << 10 ) & 0x07FF;
0000e4  7bc1              LDRB     r1,[r0,#0xf]
0000e6  1189              ASRS     r1,r1,#6
0000e8  7c02              LDRB     r2,[r0,#0x10]
0000ea  ea410182          ORR      r1,r1,r2,LSL #2
0000ee  7c42              LDRB     r2,[r0,#0x11]
0000f0  ea412182          ORR      r1,r1,r2,LSL #10
0000f4  f3c1010a          UBFX     r1,r1,#0,#11
0000f8  4a65              LDR      r2,|L1.656|
0000fa  8291              STRH     r1,[r2,#0x14]
;;;39     	CH[11] = ((int16_t)buf[17] >> 1 | ((int16_t)buf[18] << 7 )) & 0x07FF;
0000fc  7c41              LDRB     r1,[r0,#0x11]
0000fe  1049              ASRS     r1,r1,#1
000100  7c82              LDRB     r2,[r0,#0x12]
000102  ea4111c2          ORR      r1,r1,r2,LSL #7
000106  f3c1010a          UBFX     r1,r1,#0,#11
00010a  4a61              LDR      r2,|L1.656|
00010c  82d1              STRH     r1,[r2,#0x16]
;;;40     	CH[12] = ((int16_t)buf[18] >> 4 | ((int16_t)buf[19] << 4 )) & 0x07FF;
00010e  7c81              LDRB     r1,[r0,#0x12]
000110  1109              ASRS     r1,r1,#4
000112  7cc2              LDRB     r2,[r0,#0x13]
000114  ea411102          ORR      r1,r1,r2,LSL #4
000118  f3c1010a          UBFX     r1,r1,#0,#11
00011c  4a5c              LDR      r2,|L1.656|
00011e  8311              STRH     r1,[r2,#0x18]
;;;41     	CH[13] = ((int16_t)buf[19] >> 7 | ((int16_t)buf[20] << 1 )  | (int16_t)buf[21] <<  9 ) & 0x07FF;
000120  7cc1              LDRB     r1,[r0,#0x13]
000122  11c9              ASRS     r1,r1,#7
000124  7d02              LDRB     r2,[r0,#0x14]
000126  ea410142          ORR      r1,r1,r2,LSL #1
00012a  7d42              LDRB     r2,[r0,#0x15]
00012c  ea412142          ORR      r1,r1,r2,LSL #9
000130  f3c1010a          UBFX     r1,r1,#0,#11
000134  4a56              LDR      r2,|L1.656|
000136  8351              STRH     r1,[r2,#0x1a]
;;;42     	CH[14] = ((int16_t)buf[21] >> 2 | ((int16_t)buf[22] << 6 )) & 0x07FF;
000138  7d41              LDRB     r1,[r0,#0x15]
00013a  1089              ASRS     r1,r1,#2
00013c  7d82              LDRB     r2,[r0,#0x16]
00013e  ea411182          ORR      r1,r1,r2,LSL #6
000142  f3c1010a          UBFX     r1,r1,#0,#11
000146  4a52              LDR      r2,|L1.656|
000148  8391              STRH     r1,[r2,#0x1c]
;;;43     	CH[15] = ((int16_t)buf[22] >> 5 | ((int16_t)buf[23] << 3 )) & 0x07FF;
00014a  7d81              LDRB     r1,[r0,#0x16]
00014c  1149              ASRS     r1,r1,#5
00014e  7dc2              LDRB     r2,[r0,#0x17]
000150  ea4101c2          ORR      r1,r1,r2,LSL #3
000154  4a4e              LDR      r2,|L1.656|
000156  83d1              STRH     r1,[r2,#0x1e]
;;;44     	CH[16]=buf[0];
000158  7801              LDRB     r1,[r0,#0]
00015a  8411              STRH     r1,[r2,#0x20]
;;;45       CH[17]=buf[24];
00015c  7e01              LDRB     r1,[r0,#0x18]
00015e  8451              STRH     r1,[r2,#0x22]
;;;46     	
;;;47     	if(PWM_Val!=CH[2]*30){
000160  4611              MOV      r1,r2
000162  8889              LDRH     r1,[r1,#4]  ; CH
000164  ebc11101          RSB      r1,r1,r1,LSL #4
000168  4a4a              LDR      r2,|L1.660|
00016a  6812              LDR      r2,[r2,#0]  ; PWM_Val
00016c  ebb20f41          CMP      r2,r1,LSL #1
000170  d009              BEQ      |L1.390|
;;;48     		PWM_Val=CH[2]*30;
000172  4947              LDR      r1,|L1.656|
000174  8889              LDRH     r1,[r1,#4]  ; CH
000176  ebc11101          RSB      r1,r1,r1,LSL #4
00017a  0049              LSLS     r1,r1,#1
00017c  4a45              LDR      r2,|L1.660|
00017e  6011              STR      r1,[r2,#0]  ; PWM_Val
;;;49     		first=1;
000180  2101              MOVS     r1,#1
000182  4a45              LDR      r2,|L1.664|
000184  7011              STRB     r1,[r2,#0]
                  |L1.390|
;;;50     	}
;;;51     	if(CH[1]>1450&& CH[3]<1150 && CH[3]>700 && move_status!=1){
000186  4942              LDR      r1,|L1.656|
000188  8849              LDRH     r1,[r1,#2]  ; CH
00018a  f24052aa          MOV      r2,#0x5aa
00018e  4291              CMP      r1,r2
000190  dd14              BLE      |L1.444|
000192  493f              LDR      r1,|L1.656|
000194  88c9              LDRH     r1,[r1,#6]  ; CH
000196  f240427e          MOV      r2,#0x47e
00019a  4291              CMP      r1,r2
00019c  da0e              BGE      |L1.444|
00019e  493c              LDR      r1,|L1.656|
0001a0  88c9              LDRH     r1,[r1,#6]  ; CH
0001a2  f5b17f2f          CMP      r1,#0x2bc
0001a6  dd09              BLE      |L1.444|
0001a8  493c              LDR      r1,|L1.668|
0001aa  7809              LDRB     r1,[r1,#0]  ; move_status
0001ac  2901              CMP      r1,#1
0001ae  d005              BEQ      |L1.444|
;;;52     		move_status=1;
0001b0  2101              MOVS     r1,#1
0001b2  4a3a              LDR      r2,|L1.668|
0001b4  7011              STRB     r1,[r2,#0]
;;;53     		first=1;
0001b6  4a38              LDR      r2,|L1.664|
0001b8  7011              STRB     r1,[r2,#0]
0001ba  e019              B        |L1.496|
                  |L1.444|
;;;54     	}	
;;;55     	else if(CH[1]<600 && CH[3]<1150 && CH[3]>700 && move_status!=2){
0001bc  4934              LDR      r1,|L1.656|
0001be  8849              LDRH     r1,[r1,#2]  ; CH
0001c0  f5b17f16          CMP      r1,#0x258
0001c4  da14              BGE      |L1.496|
0001c6  4932              LDR      r1,|L1.656|
0001c8  88c9              LDRH     r1,[r1,#6]  ; CH
0001ca  f240427e          MOV      r2,#0x47e
0001ce  4291              CMP      r1,r2
0001d0  da0e              BGE      |L1.496|
0001d2  492f              LDR      r1,|L1.656|
0001d4  88c9              LDRH     r1,[r1,#6]  ; CH
0001d6  f5b17f2f          CMP      r1,#0x2bc
0001da  dd09              BLE      |L1.496|
0001dc  492f              LDR      r1,|L1.668|
0001de  7809              LDRB     r1,[r1,#0]  ; move_status
0001e0  2902              CMP      r1,#2
0001e2  d005              BEQ      |L1.496|
;;;56     		move_status=2;
0001e4  2102              MOVS     r1,#2
0001e6  4a2d              LDR      r2,|L1.668|
0001e8  7011              STRB     r1,[r2,#0]
;;;57     		first=1;
0001ea  2101              MOVS     r1,#1
0001ec  4a2a              LDR      r2,|L1.664|
0001ee  7011              STRB     r1,[r2,#0]
                  |L1.496|
;;;58     	}	
;;;59     	
;;;60     	if(CH[3]>1450 && move_status!=3){
0001f0  4927              LDR      r1,|L1.656|
0001f2  88c9              LDRH     r1,[r1,#6]  ; CH
0001f4  f24052aa          MOV      r2,#0x5aa
0001f8  4291              CMP      r1,r2
0001fa  dd0a              BLE      |L1.530|
0001fc  4927              LDR      r1,|L1.668|
0001fe  7809              LDRB     r1,[r1,#0]  ; move_status
000200  2903              CMP      r1,#3
000202  d006              BEQ      |L1.530|
;;;61     		move_status=3;
000204  2103              MOVS     r1,#3
000206  4a25              LDR      r2,|L1.668|
000208  7011              STRB     r1,[r2,#0]
;;;62     		first=1;
00020a  2101              MOVS     r1,#1
00020c  4a22              LDR      r2,|L1.664|
00020e  7011              STRB     r1,[r2,#0]
000210  e027              B        |L1.610|
                  |L1.530|
;;;63     	}	
;;;64     	else if(CH[3]<600 && move_status!=4){
000212  491f              LDR      r1,|L1.656|
000214  88c9              LDRH     r1,[r1,#6]  ; CH
000216  f5b17f16          CMP      r1,#0x258
00021a  da0a              BGE      |L1.562|
00021c  491f              LDR      r1,|L1.668|
00021e  7809              LDRB     r1,[r1,#0]  ; move_status
000220  2904              CMP      r1,#4
000222  d006              BEQ      |L1.562|
;;;65     		move_status=4;
000224  2104              MOVS     r1,#4
000226  4a1d              LDR      r2,|L1.668|
000228  7011              STRB     r1,[r2,#0]
;;;66     		first=1;
00022a  2101              MOVS     r1,#1
00022c  4a1a              LDR      r2,|L1.664|
00022e  7011              STRB     r1,[r2,#0]
000230  e017              B        |L1.610|
                  |L1.562|
;;;67     	}	
;;;68     	else if(CH[3]>800 && CH[3]<1100 && move_status!=1 && move_status!=2){
000232  4917              LDR      r1,|L1.656|
000234  88c9              LDRH     r1,[r1,#6]  ; CH
000236  f5b17f48          CMP      r1,#0x320
00023a  dd12              BLE      |L1.610|
00023c  4914              LDR      r1,|L1.656|
00023e  88c9              LDRH     r1,[r1,#6]  ; CH
000240  f240424c          MOV      r2,#0x44c
000244  4291              CMP      r1,r2
000246  da0c              BGE      |L1.610|
000248  4914              LDR      r1,|L1.668|
00024a  7809              LDRB     r1,[r1,#0]  ; move_status
00024c  2901              CMP      r1,#1
00024e  d008              BEQ      |L1.610|
000250  4912              LDR      r1,|L1.668|
000252  7809              LDRB     r1,[r1,#0]  ; move_status
000254  2902              CMP      r1,#2
000256  d004              BEQ      |L1.610|
;;;69     		move_status=1;
000258  2101              MOVS     r1,#1
00025a  4a10              LDR      r2,|L1.668|
00025c  7011              STRB     r1,[r2,#0]
;;;70     		first=1;
00025e  4a0e              LDR      r2,|L1.664|
000260  7011              STRB     r1,[r2,#0]
                  |L1.610|
;;;71     	}
;;;72     	if((CH[5]>1000 || CH[17]==0x15) && move_status!=0){
000262  490b              LDR      r1,|L1.656|
000264  8949              LDRH     r1,[r1,#0xa]  ; CH
000266  f5b17f7a          CMP      r1,#0x3e8
00026a  dc03              BGT      |L1.628|
00026c  4908              LDR      r1,|L1.656|
00026e  8c49              LDRH     r1,[r1,#0x22]  ; CH
000270  2915              CMP      r1,#0x15
000272  d108              BNE      |L1.646|
                  |L1.628|
000274  4909              LDR      r1,|L1.668|
000276  7809              LDRB     r1,[r1,#0]  ; move_status
000278  b129              CBZ      r1,|L1.646|
;;;73     		move_status=0;
00027a  2100              MOVS     r1,#0
00027c  4a07              LDR      r2,|L1.668|
00027e  7011              STRB     r1,[r2,#0]
;;;74     		first=1;
000280  2101              MOVS     r1,#1
000282  4a05              LDR      r2,|L1.664|
000284  7011              STRB     r1,[r2,#0]
                  |L1.646|
;;;75     	}
;;;76     }
000286  4770              BX       lr
                          ENDP

                  |L1.648|
                          DCD      0x40004400
                  |L1.652|
                          DCD      0x40011400
                  |L1.656|
                          DCD      ||CH||
                  |L1.660|
                          DCD      PWM_Val
                  |L1.664|
                          DCD      first
                  |L1.668|
                          DCD      move_status
