; generated by Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]
; commandline ArmCC [--list --debug -c --asm --interleave -o.\obj\crsf.o --asm_dir=.\list\ --list_dir=.\list\ --depend=.\obj\crsf.d --cpu=Cortex-M3 --apcs=interwork -O0 --diag_suppress=9931 -I.\FWlib\inc -I.\user -I.\CM3 -I.\dmp -I.\RTE\_STM32-FD -If:\Users\Administrator\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -If:\Users\Administrator\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.4.1\Device\Include -D__MICROLIB -D__UVISION_VERSION=530 -D_RTE_ -DSTM32F10X_MD -D_RTE_ -DUSE_STDPERIPH_DRIVER -DSTM32F10X_MD --omf_browse=.\obj\crsf.crf user\CRSF.c]
                          THUMB

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  Crc8_init PROC
;;;3      //--------------------------------------------------
;;;4      void Crc8_init(uint8_t poly)
000000  b530              PUSH     {r4,r5,lr}
;;;5      {		int shift,idx;
000002  4603              MOV      r3,r0
;;;6      		uint8_t crc;
;;;7          for (idx=0; idx<256; ++idx)
000004  2000              MOVS     r0,#0
000006  e011              B        |L1.44|
                  |L1.8|
;;;8          {
;;;9              crc = idx;
000008  b2c1              UXTB     r1,r0
;;;10             for (shift=0; shift<8; ++shift)
00000a  2200              MOVS     r2,#0
00000c  e009              B        |L1.34|
                  |L1.14|
;;;11             {
;;;12                 crc = (crc << 1) ^ ((crc & 0x80) ? poly : 0);
00000e  f0010480          AND      r4,r1,#0x80
000012  b10c              CBZ      r4,|L1.24|
000014  461c              MOV      r4,r3
000016  e000              B        |L1.26|
                  |L1.24|
000018  2400              MOVS     r4,#0
                  |L1.26|
00001a  ea840441          EOR      r4,r4,r1,LSL #1
00001e  b2e1              UXTB     r1,r4
000020  1c52              ADDS     r2,r2,#1              ;10
                  |L1.34|
000022  2a08              CMP      r2,#8                 ;10
000024  dbf3              BLT      |L1.14|
;;;13             }
;;;14             _lut[idx] = crc & 0xff;
000026  4dcc              LDR      r5,|L1.856|
000028  5429              STRB     r1,[r5,r0]
00002a  1c40              ADDS     r0,r0,#1              ;7
                  |L1.44|
00002c  28ff              CMP      r0,#0xff              ;7
00002e  ddeb              BLE      |L1.8|
;;;15         }
;;;16     }
000030  bd30              POP      {r4,r5,pc}
;;;17     
                          ENDP

                  Crc8_calc PROC
;;;18     //????crc8.cpp
;;;19     uint8_t Crc8_calc(uint8_t *data, uint8_t len)
000032  b510              PUSH     {r4,lr}
;;;20     {
000034  4602              MOV      r2,r0
;;;21         uint8_t crc = 0;
000036  2000              MOVS     r0,#0
;;;22         while (len--)
000038  e004              B        |L1.68|
                  |L1.58|
;;;23         {
;;;24             crc = _lut[crc ^ *data++];
00003a  f8123b01          LDRB     r3,[r2],#1
00003e  4043              EORS     r3,r3,r0
000040  4cc5              LDR      r4,|L1.856|
000042  5ce0              LDRB     r0,[r4,r3]
                  |L1.68|
000044  1e0b              SUBS     r3,r1,#0              ;22
000046  f1a10401          SUB      r4,r1,#1              ;22
00004a  b2e1              UXTB     r1,r4                 ;22
00004c  d1f5              BNE      |L1.58|
;;;25         }
;;;26         return crc;
;;;27     }
00004e  bd10              POP      {r4,pc}
;;;28     
                          ENDP

                  USART2_init_CRSF PROC
;;;30     
;;;31     void USART2_init_CRSF(void)
000050  b500              PUSH     {lr}
;;;32     {
000052  b087              SUB      sp,sp,#0x1c
;;;33     
;;;34         GPIO_InitTypeDef GPIO_InitStructure;
;;;35         NVIC_InitTypeDef NVIC_InitStructure;
;;;36     	  USART_InitTypeDef USART_InitStructure;
;;;37         RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); //
000054  2101              MOVS     r1,#1
000056  0448              LSLS     r0,r1,#17
000058  f7fffffe          BL       RCC_APB1PeriphClockCmd
;;;38         RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); //?? 
00005c  2101              MOVS     r1,#1
00005e  2004              MOVS     r0,#4
000060  f7fffffe          BL       RCC_APB2PeriphClockCmd
;;;39     
;;;40         USART_DeInit(USART2);  //????5  
000064  48bd              LDR      r0,|L1.860|
000066  f7fffffe          BL       USART_DeInit
;;;41         //USART2_RX   PA3
;;;42         GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
00006a  2008              MOVS     r0,#8
00006c  f8ad0018          STRH     r0,[sp,#0x18]
;;;43         GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;  
000070  2004              MOVS     r0,#4
000072  f88d001b          STRB     r0,[sp,#0x1b]
;;;44     		GPIO_Init(GPIOA, &GPIO_InitStructure);  
000076  a906              ADD      r1,sp,#0x18
000078  48b9              LDR      r0,|L1.864|
00007a  f7fffffe          BL       GPIO_Init
;;;45     
;;;46         
;;;47     
;;;48     		NVIC_InitStructure.NVIC_IRQChannel = USART2_IRQn;			     	//ô2ж
00007e  2026              MOVS     r0,#0x26
000080  f88d0014          STRB     r0,[sp,#0x14]
;;;49     		NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;	     	//ռȼ 0
000084  2000              MOVS     r0,#0
000086  f88d0015          STRB     r0,[sp,#0x15]
;;;50     		NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;				//ȼΪ0
00008a  2002              MOVS     r0,#2
00008c  f88d0016          STRB     r0,[sp,#0x16]
;;;51     		NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;					//ʹ
000090  2001              MOVS     r0,#1
000092  f88d0017          STRB     r0,[sp,#0x17]
;;;52       
;;;53     		NVIC_Init(&NVIC_InitStructure); 
000096  a805              ADD      r0,sp,#0x14
000098  f7fffffe          BL       NVIC_Init
;;;54     	
;;;55      
;;;56     		//  420K   8λ,1ֹͣλ,NOУλ,
;;;57     		USART_InitStructure.USART_BaudRate = 420000;
00009c  48b1              LDR      r0,|L1.868|
00009e  9001              STR      r0,[sp,#4]
;;;58     		USART_InitStructure.USART_WordLength = USART_WordLength_8b;
0000a0  2000              MOVS     r0,#0
0000a2  f8ad0008          STRH     r0,[sp,#8]
;;;59     		USART_InitStructure.USART_StopBits = USART_StopBits_1;
0000a6  f8ad000a          STRH     r0,[sp,#0xa]
;;;60     		USART_InitStructure.USART_Parity = USART_Parity_No;
0000aa  f8ad000c          STRH     r0,[sp,#0xc]
;;;61     		USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
0000ae  f8ad0010          STRH     r0,[sp,#0x10]
;;;62     		USART_InitStructure.USART_Mode = USART_Mode_Rx;
0000b2  2004              MOVS     r0,#4
0000b4  f8ad000e          STRH     r0,[sp,#0xe]
;;;63     
;;;64     		USART_Init(USART2, &USART_InitStructure);
0000b8  a901              ADD      r1,sp,#4
0000ba  48a8              LDR      r0,|L1.860|
0000bc  f7fffffe          BL       USART_Init
;;;65     
;;;66     		NVIC_InitStructure.NVIC_IRQChannel = USART2_IRQn;
0000c0  2026              MOVS     r0,#0x26
0000c2  f88d0014          STRB     r0,[sp,#0x14]
;;;67     		NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 4;
0000c6  2004              MOVS     r0,#4
0000c8  f88d0015          STRB     r0,[sp,#0x15]
;;;68     		NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3;
0000cc  2003              MOVS     r0,#3
0000ce  f88d0016          STRB     r0,[sp,#0x16]
;;;69     		NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
0000d2  2001              MOVS     r0,#1
0000d4  f88d0017          STRB     r0,[sp,#0x17]
;;;70     		NVIC_Init(&NVIC_InitStructure);
0000d8  a805              ADD      r0,sp,#0x14
0000da  f7fffffe          BL       NVIC_Init
;;;71     
;;;72     		USART_ITConfig(USART2, USART_IT_RXNE, ENABLE);
0000de  2201              MOVS     r2,#1
0000e0  f2405125          MOV      r1,#0x525
0000e4  489d              LDR      r0,|L1.860|
0000e6  f7fffffe          BL       USART_ITConfig
;;;73     		USART_ITConfig(USART2, USART_IT_IDLE, ENABLE);
0000ea  2201              MOVS     r2,#1
0000ec  f2404124          MOV      r1,#0x424
0000f0  489a              LDR      r0,|L1.860|
0000f2  f7fffffe          BL       USART_ITConfig
;;;74     
;;;75     		USART_Cmd(USART2, ENABLE);
0000f6  2101              MOVS     r1,#1
0000f8  4898              LDR      r0,|L1.860|
0000fa  f7fffffe          BL       USART_Cmd
;;;76     }
0000fe  b007              ADD      sp,sp,#0x1c
000100  bd00              POP      {pc}
;;;77     
                          ENDP

                  Crsf_Data_Count PROC
;;;78     
;;;79     void Crsf_Data_Count(uint8_t *buf)
000102  7901              LDRB     r1,[r0,#4]
;;;80     {
;;;81     	CH[ 0] = ((int16_t)buf[ 4] >> 0 | ((int16_t)buf[ 5] << 8 )) & 0x07FF;
000104  7942              LDRB     r2,[r0,#5]
000106  ea412102          ORR      r1,r1,r2,LSL #8
00010a  f3c1010a          UBFX     r1,r1,#0,#11
00010e  4a96              LDR      r2,|L1.872|
000110  8011              STRH     r1,[r2,#0]
;;;82     	CH[ 1] = ((int16_t)buf[ 5] >> 3 | ((int16_t)buf[ 6] << 5 )) & 0x07FF;
000112  7941              LDRB     r1,[r0,#5]
000114  10c9              ASRS     r1,r1,#3
000116  7982              LDRB     r2,[r0,#6]
000118  ea411142          ORR      r1,r1,r2,LSL #5
00011c  f3c1010a          UBFX     r1,r1,#0,#11
000120  4a91              LDR      r2,|L1.872|
000122  8051              STRH     r1,[r2,#2]
;;;83     	CH[ 2] = ((int16_t)buf[ 6] >> 6 | ((int16_t)buf[ 7] << 2 )  | (int16_t)buf[8] << 10 ) & 0x07FF;
000124  7981              LDRB     r1,[r0,#6]
000126  1189              ASRS     r1,r1,#6
000128  79c2              LDRB     r2,[r0,#7]
00012a  ea410182          ORR      r1,r1,r2,LSL #2
00012e  7a02              LDRB     r2,[r0,#8]
000130  ea412182          ORR      r1,r1,r2,LSL #10
000134  f3c1010a          UBFX     r1,r1,#0,#11
000138  4a8b              LDR      r2,|L1.872|
00013a  8091              STRH     r1,[r2,#4]
;;;84     	CH[ 3] = ((int16_t)buf[ 8] >> 1 | ((int16_t)buf[ 9] << 7 )) & 0x07FF;
00013c  7a01              LDRB     r1,[r0,#8]
00013e  1049              ASRS     r1,r1,#1
000140  7a42              LDRB     r2,[r0,#9]
000142  ea4111c2          ORR      r1,r1,r2,LSL #7
000146  f3c1010a          UBFX     r1,r1,#0,#11
00014a  4a87              LDR      r2,|L1.872|
00014c  80d1              STRH     r1,[r2,#6]
;;;85     	
;;;86     	CH[ 4] = ((int16_t)buf[ 9] >> 4 | ((int16_t)buf[ 10] << 4 )) & 0x07FF;
00014e  7a41              LDRB     r1,[r0,#9]
000150  1109              ASRS     r1,r1,#4
000152  7a82              LDRB     r2,[r0,#0xa]
000154  ea411102          ORR      r1,r1,r2,LSL #4
000158  f3c1010a          UBFX     r1,r1,#0,#11
00015c  4a82              LDR      r2,|L1.872|
00015e  8111              STRH     r1,[r2,#8]
;;;87     	CH[ 5] = ((int16_t)buf[ 10] >> 7 | ((int16_t)buf[11] << 1 )  | (int16_t)buf[12] <<  9 ) & 0x07FF;
000160  7a81              LDRB     r1,[r0,#0xa]
000162  11c9              ASRS     r1,r1,#7
000164  7ac2              LDRB     r2,[r0,#0xb]
000166  ea410142          ORR      r1,r1,r2,LSL #1
00016a  7b02              LDRB     r2,[r0,#0xc]
00016c  ea412142          ORR      r1,r1,r2,LSL #9
000170  f3c1010a          UBFX     r1,r1,#0,#11
000174  4a7c              LDR      r2,|L1.872|
000176  8151              STRH     r1,[r2,#0xa]
;;;88     	CH[ 6] = ((int16_t)buf[12] >> 2 | ((int16_t)buf[13] << 6 )) & 0x07FF;
000178  7b01              LDRB     r1,[r0,#0xc]
00017a  1089              ASRS     r1,r1,#2
00017c  7b42              LDRB     r2,[r0,#0xd]
00017e  ea411182          ORR      r1,r1,r2,LSL #6
000182  f3c1010a          UBFX     r1,r1,#0,#11
000186  4a78              LDR      r2,|L1.872|
000188  8191              STRH     r1,[r2,#0xc]
;;;89     	CH[ 7] = ((int16_t)buf[13] >> 5 | ((int16_t)buf[14] << 3 )) & 0x07FF;
00018a  7b41              LDRB     r1,[r0,#0xd]
00018c  1149              ASRS     r1,r1,#5
00018e  7b82              LDRB     r2,[r0,#0xe]
000190  ea4101c2          ORR      r1,r1,r2,LSL #3
000194  4a74              LDR      r2,|L1.872|
000196  81d1              STRH     r1,[r2,#0xe]
;;;90     	
;;;91     	CH[ 8] = ((int16_t)buf[15] << 0 | ((int16_t)buf[16] << 8 )) & 0x07FF;
000198  7bc1              LDRB     r1,[r0,#0xf]
00019a  7c02              LDRB     r2,[r0,#0x10]
00019c  ea412102          ORR      r1,r1,r2,LSL #8
0001a0  f3c1010a          UBFX     r1,r1,#0,#11
0001a4  4a70              LDR      r2,|L1.872|
0001a6  8211              STRH     r1,[r2,#0x10]
;;;92     	CH[ 9] = ((int16_t)buf[16] >> 3 | ((int16_t)buf[17] << 5 )) & 0x07FF;
0001a8  7c01              LDRB     r1,[r0,#0x10]
0001aa  10c9              ASRS     r1,r1,#3
0001ac  7c42              LDRB     r2,[r0,#0x11]
0001ae  ea411142          ORR      r1,r1,r2,LSL #5
0001b2  f3c1010a          UBFX     r1,r1,#0,#11
0001b6  4a6c              LDR      r2,|L1.872|
0001b8  8251              STRH     r1,[r2,#0x12]
;;;93     	CH[10] = ((int16_t)buf[17] >> 6 | ((int16_t)buf[18] << 2 )  | (int16_t)buf[19] << 10 ) & 0x07FF;
0001ba  7c41              LDRB     r1,[r0,#0x11]
0001bc  1189              ASRS     r1,r1,#6
0001be  7c82              LDRB     r2,[r0,#0x12]
0001c0  ea410182          ORR      r1,r1,r2,LSL #2
0001c4  7cc2              LDRB     r2,[r0,#0x13]
0001c6  ea412182          ORR      r1,r1,r2,LSL #10
0001ca  f3c1010a          UBFX     r1,r1,#0,#11
0001ce  4a66              LDR      r2,|L1.872|
0001d0  8291              STRH     r1,[r2,#0x14]
;;;94     	CH[11] = ((int16_t)buf[19] >> 1 | ((int16_t)buf[20] << 7 )) & 0x07FF;
0001d2  7cc1              LDRB     r1,[r0,#0x13]
0001d4  1049              ASRS     r1,r1,#1
0001d6  7d02              LDRB     r2,[r0,#0x14]
0001d8  ea4111c2          ORR      r1,r1,r2,LSL #7
0001dc  f3c1010a          UBFX     r1,r1,#0,#11
0001e0  4a61              LDR      r2,|L1.872|
0001e2  82d1              STRH     r1,[r2,#0x16]
;;;95     	CH[12] = ((int16_t)buf[20] >> 4 | ((int16_t)buf[21] << 4 )) & 0x07FF;
0001e4  7d01              LDRB     r1,[r0,#0x14]
0001e6  1109              ASRS     r1,r1,#4
0001e8  7d42              LDRB     r2,[r0,#0x15]
0001ea  ea411102          ORR      r1,r1,r2,LSL #4
0001ee  f3c1010a          UBFX     r1,r1,#0,#11
0001f2  4a5d              LDR      r2,|L1.872|
0001f4  8311              STRH     r1,[r2,#0x18]
;;;96     	CH[13] = ((int16_t)buf[21] >> 7 | ((int16_t)buf[22] << 1 )  | (int16_t)buf[23] <<  9 ) & 0x07FF;
0001f6  7d41              LDRB     r1,[r0,#0x15]
0001f8  11c9              ASRS     r1,r1,#7
0001fa  7d82              LDRB     r2,[r0,#0x16]
0001fc  ea410142          ORR      r1,r1,r2,LSL #1
000200  7dc2              LDRB     r2,[r0,#0x17]
000202  ea412142          ORR      r1,r1,r2,LSL #9
000206  f3c1010a          UBFX     r1,r1,#0,#11
00020a  4a57              LDR      r2,|L1.872|
00020c  8351              STRH     r1,[r2,#0x1a]
;;;97     	CH[14] = ((int16_t)buf[23] >> 2 | ((int16_t)buf[24] << 6 )) & 0x07FF;
00020e  7dc1              LDRB     r1,[r0,#0x17]
000210  1089              ASRS     r1,r1,#2
000212  7e02              LDRB     r2,[r0,#0x18]
000214  ea411182          ORR      r1,r1,r2,LSL #6
000218  f3c1010a          UBFX     r1,r1,#0,#11
00021c  4a52              LDR      r2,|L1.872|
00021e  8391              STRH     r1,[r2,#0x1c]
;;;98     	CH[15] = ((int16_t)buf[24] >> 5 | ((int16_t)buf[25] << 3 )) & 0x07FF;
000220  7e01              LDRB     r1,[r0,#0x18]
000222  1149              ASRS     r1,r1,#5
000224  7e42              LDRB     r2,[r0,#0x19]
000226  ea4101c2          ORR      r1,r1,r2,LSL #3
00022a  4a4f              LDR      r2,|L1.872|
00022c  83d1              STRH     r1,[r2,#0x1e]
;;;99     	CH[16]=buf[3];
00022e  78c1              LDRB     r1,[r0,#3]
000230  8411              STRH     r1,[r2,#0x20]
;;;100      //CH[17]=buf[24];
;;;101    	
;;;102    	
;;;103    	//CH0   193 992  1792    ҷ
;;;104    	//CH1   1811 996  196    ·
;;;105    	//CH2   182 1785    ŴС
;;;106    	//CH3   182 1785    
;;;107    	
;;;108    	
;;;109    	//CH5   191 1004 1792    SWB 
;;;110    	//CH7   191 1792    SWD 
;;;111    	
;;;112    	
;;;113    	if(PWM_Val!=CH[1]*1){
000232  4611              MOV      r1,r2
000234  8849              LDRH     r1,[r1,#2]  ; CH
000236  4a4d              LDR      r2,|L1.876|
000238  6812              LDR      r2,[r2,#0]  ; PWM_Val
00023a  4291              CMP      r1,r2
00023c  d006              BEQ      |L1.588|
;;;114    		PWM_Val=CH[1]*1;
00023e  494a              LDR      r1,|L1.872|
000240  8849              LDRH     r1,[r1,#2]  ; CH
000242  4a4a              LDR      r2,|L1.876|
000244  6011              STR      r1,[r2,#0]  ; PWM_Val
;;;115    		first=1;
000246  2101              MOVS     r1,#1
000248  4a49              LDR      r2,|L1.880|
00024a  7011              STRB     r1,[r2,#0]
                  |L1.588|
;;;116    	}
;;;117    	if(CH[2]>1450 && CH[0]<1150 && CH[0]>700 && move_status!=1){
00024c  4946              LDR      r1,|L1.872|
00024e  8889              LDRH     r1,[r1,#4]  ; CH
000250  f24052aa          MOV      r2,#0x5aa
000254  4291              CMP      r1,r2
000256  dd14              BLE      |L1.642|
000258  4943              LDR      r1,|L1.872|
00025a  8809              LDRH     r1,[r1,#0]  ; CH
00025c  f240427e          MOV      r2,#0x47e
000260  4291              CMP      r1,r2
000262  da0e              BGE      |L1.642|
000264  4940              LDR      r1,|L1.872|
000266  8809              LDRH     r1,[r1,#0]  ; CH
000268  f5b17f2f          CMP      r1,#0x2bc
00026c  dd09              BLE      |L1.642|
00026e  4941              LDR      r1,|L1.884|
000270  7809              LDRB     r1,[r1,#0]  ; move_status
000272  2901              CMP      r1,#1
000274  d005              BEQ      |L1.642|
;;;118    		move_status=1;
000276  2101              MOVS     r1,#1
000278  4a3e              LDR      r2,|L1.884|
00027a  7011              STRB     r1,[r2,#0]
;;;119    		first=1;
00027c  4a3c              LDR      r2,|L1.880|
00027e  7011              STRB     r1,[r2,#0]
000280  e019              B        |L1.694|
                  |L1.642|
;;;120    	}	
;;;121    	else if(CH[2]<600 && CH[0]<1150 && CH[0]>700 && move_status!=2){
000282  4939              LDR      r1,|L1.872|
000284  8889              LDRH     r1,[r1,#4]  ; CH
000286  f5b17f16          CMP      r1,#0x258
00028a  da14              BGE      |L1.694|
00028c  4936              LDR      r1,|L1.872|
00028e  8809              LDRH     r1,[r1,#0]  ; CH
000290  f240427e          MOV      r2,#0x47e
000294  4291              CMP      r1,r2
000296  da0e              BGE      |L1.694|
000298  4933              LDR      r1,|L1.872|
00029a  8809              LDRH     r1,[r1,#0]  ; CH
00029c  f5b17f2f          CMP      r1,#0x2bc
0002a0  dd09              BLE      |L1.694|
0002a2  4934              LDR      r1,|L1.884|
0002a4  7809              LDRB     r1,[r1,#0]  ; move_status
0002a6  2902              CMP      r1,#2
0002a8  d005              BEQ      |L1.694|
;;;122    		move_status=2;
0002aa  2102              MOVS     r1,#2
0002ac  4a31              LDR      r2,|L1.884|
0002ae  7011              STRB     r1,[r2,#0]
;;;123    		first=1;
0002b0  2101              MOVS     r1,#1
0002b2  4a2f              LDR      r2,|L1.880|
0002b4  7011              STRB     r1,[r2,#0]
                  |L1.694|
;;;124    	}	
;;;125    	
;;;126    	if(CH[0]>1400 && move_status!=4){
0002b6  492c              LDR      r1,|L1.872|
0002b8  8809              LDRH     r1,[r1,#0]  ; CH
0002ba  f5b16faf          CMP      r1,#0x578
0002be  dd0a              BLE      |L1.726|
0002c0  492c              LDR      r1,|L1.884|
0002c2  7809              LDRB     r1,[r1,#0]  ; move_status
0002c4  2904              CMP      r1,#4
0002c6  d006              BEQ      |L1.726|
;;;127    		move_status=4;                      //right
0002c8  2104              MOVS     r1,#4
0002ca  4a2a              LDR      r2,|L1.884|
0002cc  7011              STRB     r1,[r2,#0]
;;;128    		first=1;
0002ce  2101              MOVS     r1,#1
0002d0  4a27              LDR      r2,|L1.880|
0002d2  7011              STRB     r1,[r2,#0]
0002d4  e027              B        |L1.806|
                  |L1.726|
;;;129    	}	
;;;130    	else if(CH[0]<600 && move_status!=3){
0002d6  4924              LDR      r1,|L1.872|
0002d8  8809              LDRH     r1,[r1,#0]  ; CH
0002da  f5b17f16          CMP      r1,#0x258
0002de  da0a              BGE      |L1.758|
0002e0  4924              LDR      r1,|L1.884|
0002e2  7809              LDRB     r1,[r1,#0]  ; move_status
0002e4  2903              CMP      r1,#3
0002e6  d006              BEQ      |L1.758|
;;;131    		move_status=3;                       //LEFT
0002e8  2103              MOVS     r1,#3
0002ea  4a22              LDR      r2,|L1.884|
0002ec  7011              STRB     r1,[r2,#0]
;;;132    		first=1;
0002ee  2101              MOVS     r1,#1
0002f0  4a1f              LDR      r2,|L1.880|
0002f2  7011              STRB     r1,[r2,#0]
0002f4  e017              B        |L1.806|
                  |L1.758|
;;;133    	}	
;;;134    	else if(CH[0]>800 && CH[0]<1100 && move_status!=1 && move_status!=2){
0002f6  491c              LDR      r1,|L1.872|
0002f8  8809              LDRH     r1,[r1,#0]  ; CH
0002fa  f5b17f48          CMP      r1,#0x320
0002fe  dd12              BLE      |L1.806|
000300  4919              LDR      r1,|L1.872|
000302  8809              LDRH     r1,[r1,#0]  ; CH
000304  f240424c          MOV      r2,#0x44c
000308  4291              CMP      r1,r2
00030a  da0c              BGE      |L1.806|
00030c  4919              LDR      r1,|L1.884|
00030e  7809              LDRB     r1,[r1,#0]  ; move_status
000310  2901              CMP      r1,#1
000312  d008              BEQ      |L1.806|
000314  4917              LDR      r1,|L1.884|
000316  7809              LDRB     r1,[r1,#0]  ; move_status
000318  2902              CMP      r1,#2
00031a  d004              BEQ      |L1.806|
;;;135    		move_status=1;
00031c  2101              MOVS     r1,#1
00031e  4a15              LDR      r2,|L1.884|
000320  7011              STRB     r1,[r2,#0]
;;;136    		first=1;
000322  4a13              LDR      r2,|L1.880|
000324  7011              STRB     r1,[r2,#0]
                  |L1.806|
;;;137    	}
;;;138    	if((CH[1]<200 || CH[7]>1700 || CH[16]==20) && move_status!=0){     // SWD   lost link
000326  4910              LDR      r1,|L1.872|
000328  8849              LDRH     r1,[r1,#2]  ; CH
00032a  29c8              CMP      r1,#0xc8
00032c  db09              BLT      |L1.834|
00032e  490e              LDR      r1,|L1.872|
000330  89c9              LDRH     r1,[r1,#0xe]  ; CH
000332  f24062a4          MOV      r2,#0x6a4
000336  4291              CMP      r1,r2
000338  dc03              BGT      |L1.834|
00033a  490b              LDR      r1,|L1.872|
00033c  8c09              LDRH     r1,[r1,#0x20]  ; CH
00033e  2914              CMP      r1,#0x14
000340  d108              BNE      |L1.852|
                  |L1.834|
000342  490c              LDR      r1,|L1.884|
000344  7809              LDRB     r1,[r1,#0]  ; move_status
000346  b129              CBZ      r1,|L1.852|
;;;139    		move_status=0; 
000348  2100              MOVS     r1,#0
00034a  4a0a              LDR      r2,|L1.884|
00034c  7011              STRB     r1,[r2,#0]
;;;140    		first=1;
00034e  2101              MOVS     r1,#1
000350  4a07              LDR      r2,|L1.880|
000352  7011              STRB     r1,[r2,#0]
                  |L1.852|
;;;141    	}
;;;142    	
;;;143    	
;;;144    }
000354  4770              BX       lr
                          ENDP

000356  0000              DCW      0x0000
                  |L1.856|
                          DCD      _lut
                  |L1.860|
                          DCD      0x40004400
                  |L1.864|
                          DCD      0x40010800
                  |L1.868|
                          DCD      0x000668a0
                  |L1.872|
                          DCD      ||CH||
                  |L1.876|
                          DCD      PWM_Val
                  |L1.880|
                          DCD      first
                  |L1.884|
                          DCD      move_status
