; generated by ARM C/C++ Compiler with , RVCT4.0 [Build 524] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\obj\stm32f10x_rcc.o --depend=.\obj\stm32f10x_rcc.d --device=DARMSTM --apcs=interwork -O0 -I.\FWlib\inc -I.\user -I.\CM3 -Id:\Keil\ARM\INC\ST\STM32F10x -D__MICROLIB -DUSE_STDPERIPH_DRIVER -DSTM32F10X_MD --omf_browse=.\obj\stm32f10x_rcc.crf FWlib\SRC\stm32f10x_rcc.c]
                          THUMB

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  RCC_DeInit PROC
;;;216      */
;;;217    void RCC_DeInit(void)
000000  48db              LDR      r0,|L1.880|
;;;218    {
;;;219      /* Set HSION bit */
;;;220      RCC->CR |= (uint32_t)0x00000001;
000002  6800              LDR      r0,[r0,#0]
000004  f0400001          ORR      r0,r0,#1
000008  49d9              LDR      r1,|L1.880|
00000a  6008              STR      r0,[r1,#0]
;;;221    
;;;222      /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
;;;223    #ifndef STM32F10X_CL
;;;224      RCC->CFGR &= (uint32_t)0xF8FF0000;
00000c  4608              MOV      r0,r1
00000e  6840              LDR      r0,[r0,#4]
000010  49d8              LDR      r1,|L1.884|
000012  4008              ANDS     r0,r0,r1
000014  49d6              LDR      r1,|L1.880|
000016  6048              STR      r0,[r1,#4]
;;;225    #else
;;;226      RCC->CFGR &= (uint32_t)0xF0FF0000;
;;;227    #endif /* STM32F10X_CL */   
;;;228      
;;;229      /* Reset HSEON, CSSON and PLLON bits */
;;;230      RCC->CR &= (uint32_t)0xFEF6FFFF;
000018  4608              MOV      r0,r1
00001a  6800              LDR      r0,[r0,#0]
00001c  49d6              LDR      r1,|L1.888|
00001e  4008              ANDS     r0,r0,r1
000020  49d3              LDR      r1,|L1.880|
000022  6008              STR      r0,[r1,#0]
;;;231    
;;;232      /* Reset HSEBYP bit */
;;;233      RCC->CR &= (uint32_t)0xFFFBFFFF;
000024  4608              MOV      r0,r1
000026  6800              LDR      r0,[r0,#0]
000028  f4202080          BIC      r0,r0,#0x40000
00002c  6008              STR      r0,[r1,#0]
;;;234    
;;;235      /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
;;;236      RCC->CFGR &= (uint32_t)0xFF80FFFF;
00002e  4608              MOV      r0,r1
000030  6840              LDR      r0,[r0,#4]
000032  f42000fe          BIC      r0,r0,#0x7f0000
000036  6048              STR      r0,[r1,#4]
;;;237    
;;;238    #ifdef STM32F10X_CL
;;;239      /* Reset PLL2ON and PLL3ON bits */
;;;240      RCC->CR &= (uint32_t)0xEBFFFFFF;
;;;241    
;;;242      /* Disable all interrupts and clear pending bits  */
;;;243      RCC->CIR = 0x00FF0000;
;;;244    
;;;245      /* Reset CFGR2 register */
;;;246      RCC->CFGR2 = 0x00000000;
;;;247    #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
;;;248      /* Disable all interrupts and clear pending bits  */
;;;249      RCC->CIR = 0x009F0000;
;;;250    
;;;251      /* Reset CFGR2 register */
;;;252      RCC->CFGR2 = 0x00000000;      
;;;253    #else
;;;254      /* Disable all interrupts and clear pending bits  */
;;;255      RCC->CIR = 0x009F0000;
000038  f44f001f          MOV      r0,#0x9f0000
00003c  6088              STR      r0,[r1,#8]
;;;256    #endif /* STM32F10X_CL */
;;;257    
;;;258    }
00003e  4770              BX       lr
;;;259    
                          ENDP

                  RCC_HSEConfig PROC
;;;269      */
;;;270    void RCC_HSEConfig(uint32_t RCC_HSE)
000040  49cb              LDR      r1,|L1.880|
;;;271    {
;;;272      /* Check the parameters */
;;;273      assert_param(IS_RCC_HSE(RCC_HSE));
;;;274      /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
;;;275      /* Reset HSEON bit */
;;;276      RCC->CR &= CR_HSEON_Reset;
000042  6809              LDR      r1,[r1,#0]
000044  f4213180          BIC      r1,r1,#0x10000
000048  4ac9              LDR      r2,|L1.880|
00004a  6011              STR      r1,[r2,#0]
;;;277      /* Reset HSEBYP bit */
;;;278      RCC->CR &= CR_HSEBYP_Reset;
00004c  4611              MOV      r1,r2
00004e  6809              LDR      r1,[r1,#0]
000050  f4212180          BIC      r1,r1,#0x40000
000054  6011              STR      r1,[r2,#0]
;;;279      /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
;;;280      switch(RCC_HSE)
000056  f5b03f80          CMP      r0,#0x10000
00005a  d003              BEQ      |L1.100|
00005c  f5b02f80          CMP      r0,#0x40000
000060  d10e              BNE      |L1.128|
000062  e006              B        |L1.114|
                  |L1.100|
;;;281      {
;;;282        case RCC_HSE_ON:
;;;283          /* Set HSEON bit */
;;;284          RCC->CR |= CR_HSEON_Set;
000064  49c2              LDR      r1,|L1.880|
000066  6809              LDR      r1,[r1,#0]
000068  f4413180          ORR      r1,r1,#0x10000
00006c  4ac0              LDR      r2,|L1.880|
00006e  6011              STR      r1,[r2,#0]
;;;285          break;
000070  e007              B        |L1.130|
                  |L1.114|
;;;286          
;;;287        case RCC_HSE_Bypass:
;;;288          /* Set HSEBYP and HSEON bits */
;;;289          RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
000072  49bf              LDR      r1,|L1.880|
000074  6809              LDR      r1,[r1,#0]
000076  f44121a0          ORR      r1,r1,#0x50000
00007a  4abd              LDR      r2,|L1.880|
00007c  6011              STR      r1,[r2,#0]
;;;290          break;
00007e  e000              B        |L1.130|
                  |L1.128|
;;;291          
;;;292        default:
;;;293          break;
000080  bf00              NOP      
                  |L1.130|
000082  bf00              NOP                            ;285
;;;294      }
;;;295    }
000084  4770              BX       lr
;;;296    
                          ENDP

                  RCC_GetFlagStatus PROC
;;;1325     */
;;;1326   FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
000086  b510              PUSH     {r4,lr}
;;;1327   {
000088  4601              MOV      r1,r0
;;;1328     uint32_t tmp = 0;
00008a  2200              MOVS     r2,#0
;;;1329     uint32_t statusreg = 0;
00008c  2300              MOVS     r3,#0
;;;1330     FlagStatus bitstatus = RESET;
00008e  2000              MOVS     r0,#0
;;;1331     /* Check the parameters */
;;;1332     assert_param(IS_RCC_FLAG(RCC_FLAG));
;;;1333   
;;;1334     /* Get the RCC register index */
;;;1335     tmp = RCC_FLAG >> 5;
000090  114a              ASRS     r2,r1,#5
;;;1336     if (tmp == 1)               /* The flag to check is in CR register */
000092  2a01              CMP      r2,#1
000094  d102              BNE      |L1.156|
;;;1337     {
;;;1338       statusreg = RCC->CR;
000096  4cb6              LDR      r4,|L1.880|
000098  6823              LDR      r3,[r4,#0]
00009a  e006              B        |L1.170|
                  |L1.156|
;;;1339     }
;;;1340     else if (tmp == 2)          /* The flag to check is in BDCR register */
00009c  2a02              CMP      r2,#2
00009e  d102              BNE      |L1.166|
;;;1341     {
;;;1342       statusreg = RCC->BDCR;
0000a0  4cb3              LDR      r4,|L1.880|
0000a2  6a23              LDR      r3,[r4,#0x20]
0000a4  e001              B        |L1.170|
                  |L1.166|
;;;1343     }
;;;1344     else                       /* The flag to check is in CSR register */
;;;1345     {
;;;1346       statusreg = RCC->CSR;
0000a6  4cb2              LDR      r4,|L1.880|
0000a8  6a63              LDR      r3,[r4,#0x24]
                  |L1.170|
;;;1347     }
;;;1348   
;;;1349     /* Get the flag position */
;;;1350     tmp = RCC_FLAG & FLAG_Mask;
0000aa  f001021f          AND      r2,r1,#0x1f
;;;1351     if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
0000ae  2401              MOVS     r4,#1
0000b0  4094              LSLS     r4,r4,r2
0000b2  421c              TST      r4,r3
0000b4  d001              BEQ      |L1.186|
;;;1352     {
;;;1353       bitstatus = SET;
0000b6  2001              MOVS     r0,#1
0000b8  e000              B        |L1.188|
                  |L1.186|
;;;1354     }
;;;1355     else
;;;1356     {
;;;1357       bitstatus = RESET;
0000ba  2000              MOVS     r0,#0
                  |L1.188|
;;;1358     }
;;;1359   
;;;1360     /* Return the flag status */
;;;1361     return bitstatus;
;;;1362   }
0000bc  bd10              POP      {r4,pc}
;;;1363   
                          ENDP

                  RCC_WaitForHSEStartUp PROC
;;;303      */
;;;304    ErrorStatus RCC_WaitForHSEStartUp(void)
0000be  b570              PUSH     {r4-r6,lr}
;;;305    {
;;;306      __IO uint32_t StartUpCounter = 0;
0000c0  2400              MOVS     r4,#0
;;;307      ErrorStatus status = ERROR;
0000c2  2500              MOVS     r5,#0
;;;308      FlagStatus HSEStatus = RESET;
0000c4  2600              MOVS     r6,#0
;;;309      
;;;310      /* Wait till HSE is ready and if Time out is reached exit */
;;;311      do
0000c6  bf00              NOP      
                  |L1.200|
;;;312      {
;;;313        HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
0000c8  2031              MOVS     r0,#0x31
0000ca  f7fffffe          BL       RCC_GetFlagStatus
0000ce  4606              MOV      r6,r0
;;;314        StartUpCounter++;  
0000d0  1c64              ADDS     r4,r4,#1
;;;315      } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
0000d2  f5b46fa0          CMP      r4,#0x500
0000d6  d001              BEQ      |L1.220|
0000d8  2e00              CMP      r6,#0
0000da  d0f5              BEQ      |L1.200|
                  |L1.220|
;;;316      
;;;317      if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
0000dc  2031              MOVS     r0,#0x31
0000de  f7fffffe          BL       RCC_GetFlagStatus
0000e2  b108              CBZ      r0,|L1.232|
;;;318      {
;;;319        status = SUCCESS;
0000e4  2501              MOVS     r5,#1
0000e6  e000              B        |L1.234|
                  |L1.232|
;;;320      }
;;;321      else
;;;322      {
;;;323        status = ERROR;
0000e8  2500              MOVS     r5,#0
                  |L1.234|
;;;324      }  
;;;325      return (status);
0000ea  4628              MOV      r0,r5
;;;326    }
0000ec  bd70              POP      {r4-r6,pc}
;;;327    
                          ENDP

                  RCC_AdjustHSICalibrationValue PROC
;;;333      */
;;;334    void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
0000ee  2100              MOVS     r1,#0
;;;335    {
;;;336      uint32_t tmpreg = 0;
;;;337      /* Check the parameters */
;;;338      assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
;;;339      tmpreg = RCC->CR;
0000f0  4a9f              LDR      r2,|L1.880|
0000f2  6811              LDR      r1,[r2,#0]
;;;340      /* Clear HSITRIM[4:0] bits */
;;;341      tmpreg &= CR_HSITRIM_Mask;
0000f4  f02101f8          BIC      r1,r1,#0xf8
;;;342      /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
;;;343      tmpreg |= (uint32_t)HSICalibrationValue << 3;
0000f8  ea4101c0          ORR      r1,r1,r0,LSL #3
;;;344      /* Store the new value */
;;;345      RCC->CR = tmpreg;
0000fc  6011              STR      r1,[r2,#0]
;;;346    }
0000fe  4770              BX       lr
;;;347    
                          ENDP

                  RCC_HSICmd PROC
;;;353      */
;;;354    void RCC_HSICmd(FunctionalState NewState)
000100  499e              LDR      r1,|L1.892|
;;;355    {
;;;356      /* Check the parameters */
;;;357      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;358      *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
000102  6008              STR      r0,[r1,#0]
;;;359    }
000104  4770              BX       lr
;;;360    
                          ENDP

                  RCC_PLLConfig PROC
;;;377      */
;;;378    void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
000106  2200              MOVS     r2,#0
;;;379    {
;;;380      uint32_t tmpreg = 0;
;;;381    
;;;382      /* Check the parameters */
;;;383      assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
;;;384      assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
;;;385    
;;;386      tmpreg = RCC->CFGR;
000108  4b99              LDR      r3,|L1.880|
00010a  685a              LDR      r2,[r3,#4]
;;;387      /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
;;;388      tmpreg &= CFGR_PLL_Mask;
00010c  f422127c          BIC      r2,r2,#0x3f0000
;;;389      /* Set the PLL configuration bits */
;;;390      tmpreg |= RCC_PLLSource | RCC_PLLMul;
000110  ea400301          ORR      r3,r0,r1
000114  431a              ORRS     r2,r2,r3
;;;391      /* Store the new value */
;;;392      RCC->CFGR = tmpreg;
000116  4b96              LDR      r3,|L1.880|
000118  605a              STR      r2,[r3,#4]
;;;393    }
00011a  4770              BX       lr
;;;394    
                          ENDP

                  RCC_PLLCmd PROC
;;;400      */
;;;401    void RCC_PLLCmd(FunctionalState NewState)
00011c  4997              LDR      r1,|L1.892|
;;;402    {
;;;403      /* Check the parameters */
;;;404      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;405    
;;;406      *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
00011e  6608              STR      r0,[r1,#0x60]
;;;407    }
000120  4770              BX       lr
;;;408    
                          ENDP

                  RCC_SYSCLKConfig PROC
;;;563      */
;;;564    void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
000122  2100              MOVS     r1,#0
;;;565    {
;;;566      uint32_t tmpreg = 0;
;;;567      /* Check the parameters */
;;;568      assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
;;;569      tmpreg = RCC->CFGR;
000124  4a92              LDR      r2,|L1.880|
000126  6851              LDR      r1,[r2,#4]
;;;570      /* Clear SW[1:0] bits */
;;;571      tmpreg &= CFGR_SW_Mask;
000128  f0210103          BIC      r1,r1,#3
;;;572      /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
;;;573      tmpreg |= RCC_SYSCLKSource;
00012c  4301              ORRS     r1,r1,r0
;;;574      /* Store the new value */
;;;575      RCC->CFGR = tmpreg;
00012e  6051              STR      r1,[r2,#4]
;;;576    }
000130  4770              BX       lr
;;;577    
                          ENDP

                  RCC_GetSYSCLKSource PROC
;;;586      */
;;;587    uint8_t RCC_GetSYSCLKSource(void)
000132  488f              LDR      r0,|L1.880|
;;;588    {
;;;589      return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));
000134  6840              LDR      r0,[r0,#4]
000136  f000000c          AND      r0,r0,#0xc
;;;590    }
00013a  4770              BX       lr
;;;591    
                          ENDP

                  RCC_HCLKConfig PROC
;;;607      */
;;;608    void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
00013c  2100              MOVS     r1,#0
;;;609    {
;;;610      uint32_t tmpreg = 0;
;;;611      /* Check the parameters */
;;;612      assert_param(IS_RCC_HCLK(RCC_SYSCLK));
;;;613      tmpreg = RCC->CFGR;
00013e  4a8c              LDR      r2,|L1.880|
000140  6851              LDR      r1,[r2,#4]
;;;614      /* Clear HPRE[3:0] bits */
;;;615      tmpreg &= CFGR_HPRE_Reset_Mask;
000142  f02101f0          BIC      r1,r1,#0xf0
;;;616      /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
;;;617      tmpreg |= RCC_SYSCLK;
000146  4301              ORRS     r1,r1,r0
;;;618      /* Store the new value */
;;;619      RCC->CFGR = tmpreg;
000148  6051              STR      r1,[r2,#4]
;;;620    }
00014a  4770              BX       lr
;;;621    
                          ENDP

                  RCC_PCLK1Config PROC
;;;633      */
;;;634    void RCC_PCLK1Config(uint32_t RCC_HCLK)
00014c  2100              MOVS     r1,#0
;;;635    {
;;;636      uint32_t tmpreg = 0;
;;;637      /* Check the parameters */
;;;638      assert_param(IS_RCC_PCLK(RCC_HCLK));
;;;639      tmpreg = RCC->CFGR;
00014e  4a88              LDR      r2,|L1.880|
000150  6851              LDR      r1,[r2,#4]
;;;640      /* Clear PPRE1[2:0] bits */
;;;641      tmpreg &= CFGR_PPRE1_Reset_Mask;
000152  f42161e0          BIC      r1,r1,#0x700
;;;642      /* Set PPRE1[2:0] bits according to RCC_HCLK value */
;;;643      tmpreg |= RCC_HCLK;
000156  4301              ORRS     r1,r1,r0
;;;644      /* Store the new value */
;;;645      RCC->CFGR = tmpreg;
000158  6051              STR      r1,[r2,#4]
;;;646    }
00015a  4770              BX       lr
;;;647    
                          ENDP

                  RCC_PCLK2Config PROC
;;;659      */
;;;660    void RCC_PCLK2Config(uint32_t RCC_HCLK)
00015c  2100              MOVS     r1,#0
;;;661    {
;;;662      uint32_t tmpreg = 0;
;;;663      /* Check the parameters */
;;;664      assert_param(IS_RCC_PCLK(RCC_HCLK));
;;;665      tmpreg = RCC->CFGR;
00015e  4a84              LDR      r2,|L1.880|
000160  6851              LDR      r1,[r2,#4]
;;;666      /* Clear PPRE2[2:0] bits */
;;;667      tmpreg &= CFGR_PPRE2_Reset_Mask;
000162  f4215160          BIC      r1,r1,#0x3800
;;;668      /* Set PPRE2[2:0] bits according to RCC_HCLK value */
;;;669      tmpreg |= RCC_HCLK << 3;
000166  ea4101c0          ORR      r1,r1,r0,LSL #3
;;;670      /* Store the new value */
;;;671      RCC->CFGR = tmpreg;
00016a  6051              STR      r1,[r2,#4]
;;;672    }
00016c  4770              BX       lr
;;;673    
                          ENDP

                  RCC_ITConfig PROC
;;;699      */
;;;700    void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
00016e  b129              CBZ      r1,|L1.380|
;;;701    {
;;;702      /* Check the parameters */
;;;703      assert_param(IS_RCC_IT(RCC_IT));
;;;704      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;705      if (NewState != DISABLE)
;;;706      {
;;;707        /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */
;;;708        *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
000170  4a7f              LDR      r2,|L1.880|
000172  7a52              LDRB     r2,[r2,#9]
000174  4302              ORRS     r2,r2,r0
000176  4b7e              LDR      r3,|L1.880|
000178  725a              STRB     r2,[r3,#9]
00017a  e006              B        |L1.394|
                  |L1.380|
;;;709      }
;;;710      else
;;;711      {
;;;712        /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */
;;;713        *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
00017c  4a7c              LDR      r2,|L1.880|
00017e  7a52              LDRB     r2,[r2,#9]
000180  43c3              MVNS     r3,r0
000182  b2db              UXTB     r3,r3
000184  401a              ANDS     r2,r2,r3
000186  4b7a              LDR      r3,|L1.880|
000188  725a              STRB     r2,[r3,#9]
                  |L1.394|
;;;714      }
;;;715    }
00018a  4770              BX       lr
;;;716    
                          ENDP

                  RCC_USBCLKConfig PROC
;;;727      */
;;;728    void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
00018c  497b              LDR      r1,|L1.892|
;;;729    {
;;;730      /* Check the parameters */
;;;731      assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
;;;732    
;;;733      *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;
00018e  31d8              ADDS     r1,r1,#0xd8
000190  6008              STR      r0,[r1,#0]
;;;734    }
000192  4770              BX       lr
;;;735    #else
                          ENDP

                  RCC_ADCCLKConfig PROC
;;;765      */
;;;766    void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
000194  2100              MOVS     r1,#0
;;;767    {
;;;768      uint32_t tmpreg = 0;
;;;769      /* Check the parameters */
;;;770      assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
;;;771      tmpreg = RCC->CFGR;
000196  4a76              LDR      r2,|L1.880|
000198  6851              LDR      r1,[r2,#4]
;;;772      /* Clear ADCPRE[1:0] bits */
;;;773      tmpreg &= CFGR_ADCPRE_Reset_Mask;
00019a  f4214140          BIC      r1,r1,#0xc000
;;;774      /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
;;;775      tmpreg |= RCC_PCLK2;
00019e  4301              ORRS     r1,r1,r0
;;;776      /* Store the new value */
;;;777      RCC->CFGR = tmpreg;
0001a0  6051              STR      r1,[r2,#4]
;;;778    }
0001a2  4770              BX       lr
;;;779    
                          ENDP

                  RCC_LSEConfig PROC
;;;828      */
;;;829    void RCC_LSEConfig(uint8_t RCC_LSE)
0001a4  2100              MOVS     r1,#0
;;;830    {
;;;831      /* Check the parameters */
;;;832      assert_param(IS_RCC_LSE(RCC_LSE));
;;;833      /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
;;;834      /* Reset LSEON bit */
;;;835      *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
0001a6  4a72              LDR      r2,|L1.880|
0001a8  3220              ADDS     r2,r2,#0x20
0001aa  7011              STRB     r1,[r2,#0]
;;;836      /* Reset LSEBYP bit */
;;;837      *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
0001ac  4a70              LDR      r2,|L1.880|
0001ae  f8821020          STRB     r1,[r2,#0x20]
;;;838      /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
;;;839      switch(RCC_LSE)
0001b2  2801              CMP      r0,#1
0001b4  d002              BEQ      |L1.444|
0001b6  2804              CMP      r0,#4
0001b8  d10a              BNE      |L1.464|
0001ba  e004              B        |L1.454|
                  |L1.444|
;;;840      {
;;;841        case RCC_LSE_ON:
;;;842          /* Set LSEON bit */
;;;843          *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
0001bc  2101              MOVS     r1,#1
0001be  4a6c              LDR      r2,|L1.880|
0001c0  3220              ADDS     r2,r2,#0x20
0001c2  7011              STRB     r1,[r2,#0]
;;;844          break;
0001c4  e005              B        |L1.466|
                  |L1.454|
;;;845          
;;;846        case RCC_LSE_Bypass:
;;;847          /* Set LSEBYP and LSEON bits */
;;;848          *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
0001c6  2105              MOVS     r1,#5
0001c8  4a69              LDR      r2,|L1.880|
0001ca  3220              ADDS     r2,r2,#0x20
0001cc  7011              STRB     r1,[r2,#0]
;;;849          break;            
0001ce  e000              B        |L1.466|
                  |L1.464|
;;;850          
;;;851        default:
;;;852          break;      
0001d0  bf00              NOP      
                  |L1.466|
0001d2  bf00              NOP                            ;844
;;;853      }
;;;854    }
0001d4  4770              BX       lr
;;;855    
                          ENDP

                  RCC_LSICmd PROC
;;;861      */
;;;862    void RCC_LSICmd(FunctionalState NewState)
0001d6  496a              LDR      r1,|L1.896|
;;;863    {
;;;864      /* Check the parameters */
;;;865      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;866      *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
0001d8  6008              STR      r0,[r1,#0]
;;;867    }
0001da  4770              BX       lr
;;;868    
                          ENDP

                  RCC_RTCCLKConfig PROC
;;;878      */
;;;879    void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
0001dc  4964              LDR      r1,|L1.880|
;;;880    {
;;;881      /* Check the parameters */
;;;882      assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
;;;883      /* Select the RTC clock source */
;;;884      RCC->BDCR |= RCC_RTCCLKSource;
0001de  6a09              LDR      r1,[r1,#0x20]
0001e0  4301              ORRS     r1,r1,r0
0001e2  4a63              LDR      r2,|L1.880|
0001e4  6211              STR      r1,[r2,#0x20]
;;;885    }
0001e6  4770              BX       lr
;;;886    
                          ENDP

                  RCC_RTCCLKCmd PROC
;;;892      */
;;;893    void RCC_RTCCLKCmd(FunctionalState NewState)
0001e8  4965              LDR      r1,|L1.896|
;;;894    {
;;;895      /* Check the parameters */
;;;896      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;897      *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
0001ea  3944              SUBS     r1,r1,#0x44
0001ec  6008              STR      r0,[r1,#0]
;;;898    }
0001ee  4770              BX       lr
;;;899    
                          ENDP

                  RCC_GetClocksFreq PROC
;;;907      */
;;;908    void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
0001f0  b530              PUSH     {r4,r5,lr}
;;;909    {
;;;910      uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
0001f2  2100              MOVS     r1,#0
0001f4  2200              MOVS     r2,#0
0001f6  2300              MOVS     r3,#0
0001f8  2400              MOVS     r4,#0
;;;911    
;;;912    #ifdef  STM32F10X_CL
;;;913      uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
;;;914    #endif /* STM32F10X_CL */
;;;915    
;;;916    #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
;;;917      uint32_t prediv1factor = 0;
;;;918    #endif
;;;919        
;;;920      /* Get SYSCLK source -------------------------------------------------------*/
;;;921      tmp = RCC->CFGR & CFGR_SWS_Mask;
0001fa  4d5d              LDR      r5,|L1.880|
0001fc  686d              LDR      r5,[r5,#4]
0001fe  f005010c          AND      r1,r5,#0xc
;;;922      
;;;923      switch (tmp)
000202  b121              CBZ      r1,|L1.526|
000204  2904              CMP      r1,#4
000206  d005              BEQ      |L1.532|
000208  2908              CMP      r1,#8
00020a  d123              BNE      |L1.596|
00020c  e005              B        |L1.538|
                  |L1.526|
;;;924      {
;;;925        case 0x00:  /* HSI used as system clock */
;;;926          RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
00020e  4d5d              LDR      r5,|L1.900|
000210  6005              STR      r5,[r0,#0]
;;;927          break;
000212  e022              B        |L1.602|
                  |L1.532|
;;;928        case 0x04:  /* HSE used as system clock */
;;;929          RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
000214  4d5b              LDR      r5,|L1.900|
000216  6005              STR      r5,[r0,#0]
;;;930          break;
000218  e01f              B        |L1.602|
                  |L1.538|
;;;931        case 0x08:  /* PLL used as system clock */
;;;932    
;;;933          /* Get PLL clock source and multiplication factor ----------------------*/
;;;934          pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
00021a  4d55              LDR      r5,|L1.880|
00021c  686d              LDR      r5,[r5,#4]
00021e  f4051270          AND      r2,r5,#0x3c0000
;;;935          pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
000222  4d53              LDR      r5,|L1.880|
000224  686d              LDR      r5,[r5,#4]
000226  f4053380          AND      r3,r5,#0x10000
;;;936          
;;;937    #ifndef STM32F10X_CL      
;;;938          pllmull = ( pllmull >> 18) + 2;
00022a  2502              MOVS     r5,#2
00022c  eb054292          ADD      r2,r5,r2,LSR #18
;;;939          
;;;940          if (pllsource == 0x00)
000230  b91b              CBNZ     r3,|L1.570|
;;;941          {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
;;;942            RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
000232  4d55              LDR      r5,|L1.904|
000234  4355              MULS     r5,r2,r5
000236  6005              STR      r5,[r0,#0]
000238  e00b              B        |L1.594|
                  |L1.570|
;;;943          }
;;;944          else
;;;945          {
;;;946     #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
;;;947           prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
;;;948           /* HSE oscillator clock selected as PREDIV1 clock entry */
;;;949           RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; 
;;;950     #else
;;;951            /* HSE selected as PLL clock entry */
;;;952            if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
00023a  4d4d              LDR      r5,|L1.880|
00023c  686d              LDR      r5,[r5,#4]
00023e  f4153f00          TST      r5,#0x20000
000242  d003              BEQ      |L1.588|
;;;953            {/* HSE oscillator clock divided by 2 */
;;;954              RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
000244  4d50              LDR      r5,|L1.904|
000246  4355              MULS     r5,r2,r5
000248  6005              STR      r5,[r0,#0]
00024a  e002              B        |L1.594|
                  |L1.588|
;;;955            }
;;;956            else
;;;957            {
;;;958              RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
00024c  4d4d              LDR      r5,|L1.900|
00024e  4355              MULS     r5,r2,r5
000250  6005              STR      r5,[r0,#0]
                  |L1.594|
;;;959            }
;;;960     #endif
;;;961          }
;;;962    #else
;;;963          pllmull = pllmull >> 18;
;;;964          
;;;965          if (pllmull != 0x0D)
;;;966          {
;;;967             pllmull += 2;
;;;968          }
;;;969          else
;;;970          { /* PLL multiplication factor = PLL input clock * 6.5 */
;;;971            pllmull = 13 / 2; 
;;;972          }
;;;973                
;;;974          if (pllsource == 0x00)
;;;975          {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
;;;976            RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
;;;977          }
;;;978          else
;;;979          {/* PREDIV1 selected as PLL clock entry */
;;;980            
;;;981            /* Get PREDIV1 clock source and division factor */
;;;982            prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC;
;;;983            prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
;;;984            
;;;985            if (prediv1source == 0)
;;;986            { /* HSE oscillator clock selected as PREDIV1 clock entry */
;;;987              RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull;          
;;;988            }
;;;989            else
;;;990            {/* PLL2 clock selected as PREDIV1 clock entry */
;;;991              
;;;992              /* Get PREDIV2 division factor and PLL2 multiplication factor */
;;;993              prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;
;;;994              pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; 
;;;995              RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
;;;996            }
;;;997          }
;;;998    #endif /* STM32F10X_CL */ 
;;;999          break;
000252  e002              B        |L1.602|
                  |L1.596|
;;;1000   
;;;1001       default:
;;;1002         RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
000254  4d4b              LDR      r5,|L1.900|
000256  6005              STR      r5,[r0,#0]
;;;1003         break;
000258  bf00              NOP      
                  |L1.602|
00025a  bf00              NOP                            ;927
;;;1004     }
;;;1005   
;;;1006     /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
;;;1007     /* Get HCLK prescaler */
;;;1008     tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
00025c  4d44              LDR      r5,|L1.880|
00025e  686d              LDR      r5,[r5,#4]
000260  f00501f0          AND      r1,r5,#0xf0
;;;1009     tmp = tmp >> 4;
000264  0909              LSRS     r1,r1,#4
;;;1010     presc = APBAHBPrescTable[tmp];
000266  4d49              LDR      r5,|L1.908|
000268  5c6c              LDRB     r4,[r5,r1]
;;;1011     /* HCLK clock frequency */
;;;1012     RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
00026a  6805              LDR      r5,[r0,#0]
00026c  40e5              LSRS     r5,r5,r4
00026e  6045              STR      r5,[r0,#4]
;;;1013     /* Get PCLK1 prescaler */
;;;1014     tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
000270  4d3f              LDR      r5,|L1.880|
000272  686d              LDR      r5,[r5,#4]
000274  f40561e0          AND      r1,r5,#0x700
;;;1015     tmp = tmp >> 8;
000278  0a09              LSRS     r1,r1,#8
;;;1016     presc = APBAHBPrescTable[tmp];
00027a  4d44              LDR      r5,|L1.908|
00027c  5c6c              LDRB     r4,[r5,r1]
;;;1017     /* PCLK1 clock frequency */
;;;1018     RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
00027e  6845              LDR      r5,[r0,#4]
000280  40e5              LSRS     r5,r5,r4
000282  6085              STR      r5,[r0,#8]
;;;1019     /* Get PCLK2 prescaler */
;;;1020     tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
000284  4d3a              LDR      r5,|L1.880|
000286  686d              LDR      r5,[r5,#4]
000288  f4055160          AND      r1,r5,#0x3800
;;;1021     tmp = tmp >> 11;
00028c  0ac9              LSRS     r1,r1,#11
;;;1022     presc = APBAHBPrescTable[tmp];
00028e  4d3f              LDR      r5,|L1.908|
000290  5c6c              LDRB     r4,[r5,r1]
;;;1023     /* PCLK2 clock frequency */
;;;1024     RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
000292  6845              LDR      r5,[r0,#4]
000294  40e5              LSRS     r5,r5,r4
000296  60c5              STR      r5,[r0,#0xc]
;;;1025     /* Get ADCCLK prescaler */
;;;1026     tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
000298  4d35              LDR      r5,|L1.880|
00029a  686d              LDR      r5,[r5,#4]
00029c  f4054140          AND      r1,r5,#0xc000
;;;1027     tmp = tmp >> 14;
0002a0  0b89              LSRS     r1,r1,#14
;;;1028     presc = ADCPrescTable[tmp];
0002a2  4d3a              LDR      r5,|L1.908|
0002a4  3510              ADDS     r5,r5,#0x10
0002a6  5c6c              LDRB     r4,[r5,r1]
;;;1029     /* ADCCLK clock frequency */
;;;1030     RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
0002a8  68c5              LDR      r5,[r0,#0xc]
0002aa  fbb5f5f4          UDIV     r5,r5,r4
0002ae  6105              STR      r5,[r0,#0x10]
;;;1031   }
0002b0  bd30              POP      {r4,r5,pc}
;;;1032   
                          ENDP

                  RCC_AHBPeriphClockCmd PROC
;;;1063     */
;;;1064   void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
0002b2  b129              CBZ      r1,|L1.704|
;;;1065   {
;;;1066     /* Check the parameters */
;;;1067     assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
;;;1068     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1069   
;;;1070     if (NewState != DISABLE)
;;;1071     {
;;;1072       RCC->AHBENR |= RCC_AHBPeriph;
0002b4  4a2e              LDR      r2,|L1.880|
0002b6  6952              LDR      r2,[r2,#0x14]
0002b8  4302              ORRS     r2,r2,r0
0002ba  4b2d              LDR      r3,|L1.880|
0002bc  615a              STR      r2,[r3,#0x14]
0002be  e004              B        |L1.714|
                  |L1.704|
;;;1073     }
;;;1074     else
;;;1075     {
;;;1076       RCC->AHBENR &= ~RCC_AHBPeriph;
0002c0  4a2b              LDR      r2,|L1.880|
0002c2  6952              LDR      r2,[r2,#0x14]
0002c4  4382              BICS     r2,r2,r0
0002c6  4b2a              LDR      r3,|L1.880|
0002c8  615a              STR      r2,[r3,#0x14]
                  |L1.714|
;;;1077     }
;;;1078   }
0002ca  4770              BX       lr
;;;1079   
                          ENDP

                  RCC_APB2PeriphClockCmd PROC
;;;1094     */
;;;1095   void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
0002cc  b129              CBZ      r1,|L1.730|
;;;1096   {
;;;1097     /* Check the parameters */
;;;1098     assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
;;;1099     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1100     if (NewState != DISABLE)
;;;1101     {
;;;1102       RCC->APB2ENR |= RCC_APB2Periph;
0002ce  4a28              LDR      r2,|L1.880|
0002d0  6992              LDR      r2,[r2,#0x18]
0002d2  4302              ORRS     r2,r2,r0
0002d4  4b26              LDR      r3,|L1.880|
0002d6  619a              STR      r2,[r3,#0x18]
0002d8  e004              B        |L1.740|
                  |L1.730|
;;;1103     }
;;;1104     else
;;;1105     {
;;;1106       RCC->APB2ENR &= ~RCC_APB2Periph;
0002da  4a25              LDR      r2,|L1.880|
0002dc  6992              LDR      r2,[r2,#0x18]
0002de  4382              BICS     r2,r2,r0
0002e0  4b23              LDR      r3,|L1.880|
0002e2  619a              STR      r2,[r3,#0x18]
                  |L1.740|
;;;1107     }
;;;1108   }
0002e4  4770              BX       lr
;;;1109   
                          ENDP

                  RCC_APB1PeriphClockCmd PROC
;;;1125     */
;;;1126   void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
0002e6  b129              CBZ      r1,|L1.756|
;;;1127   {
;;;1128     /* Check the parameters */
;;;1129     assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
;;;1130     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1131     if (NewState != DISABLE)
;;;1132     {
;;;1133       RCC->APB1ENR |= RCC_APB1Periph;
0002e8  4a21              LDR      r2,|L1.880|
0002ea  69d2              LDR      r2,[r2,#0x1c]
0002ec  4302              ORRS     r2,r2,r0
0002ee  4b20              LDR      r3,|L1.880|
0002f0  61da              STR      r2,[r3,#0x1c]
0002f2  e004              B        |L1.766|
                  |L1.756|
;;;1134     }
;;;1135     else
;;;1136     {
;;;1137       RCC->APB1ENR &= ~RCC_APB1Periph;
0002f4  4a1e              LDR      r2,|L1.880|
0002f6  69d2              LDR      r2,[r2,#0x1c]
0002f8  4382              BICS     r2,r2,r0
0002fa  4b1d              LDR      r3,|L1.880|
0002fc  61da              STR      r2,[r3,#0x1c]
                  |L1.766|
;;;1138     }
;;;1139   }
0002fe  4770              BX       lr
;;;1140   
                          ENDP

                  RCC_APB2PeriphResetCmd PROC
;;;1184     */
;;;1185   void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
000300  b129              CBZ      r1,|L1.782|
;;;1186   {
;;;1187     /* Check the parameters */
;;;1188     assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
;;;1189     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1190     if (NewState != DISABLE)
;;;1191     {
;;;1192       RCC->APB2RSTR |= RCC_APB2Periph;
000302  4a1b              LDR      r2,|L1.880|
000304  68d2              LDR      r2,[r2,#0xc]
000306  4302              ORRS     r2,r2,r0
000308  4b19              LDR      r3,|L1.880|
00030a  60da              STR      r2,[r3,#0xc]
00030c  e004              B        |L1.792|
                  |L1.782|
;;;1193     }
;;;1194     else
;;;1195     {
;;;1196       RCC->APB2RSTR &= ~RCC_APB2Periph;
00030e  4a18              LDR      r2,|L1.880|
000310  68d2              LDR      r2,[r2,#0xc]
000312  4382              BICS     r2,r2,r0
000314  4b16              LDR      r3,|L1.880|
000316  60da              STR      r2,[r3,#0xc]
                  |L1.792|
;;;1197     }
;;;1198   }
000318  4770              BX       lr
;;;1199   
                          ENDP

                  RCC_APB1PeriphResetCmd PROC
;;;1215     */
;;;1216   void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
00031a  b129              CBZ      r1,|L1.808|
;;;1217   {
;;;1218     /* Check the parameters */
;;;1219     assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
;;;1220     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1221     if (NewState != DISABLE)
;;;1222     {
;;;1223       RCC->APB1RSTR |= RCC_APB1Periph;
00031c  4a14              LDR      r2,|L1.880|
00031e  6912              LDR      r2,[r2,#0x10]
000320  4302              ORRS     r2,r2,r0
000322  4b13              LDR      r3,|L1.880|
000324  611a              STR      r2,[r3,#0x10]
000326  e004              B        |L1.818|
                  |L1.808|
;;;1224     }
;;;1225     else
;;;1226     {
;;;1227       RCC->APB1RSTR &= ~RCC_APB1Periph;
000328  4a11              LDR      r2,|L1.880|
00032a  6912              LDR      r2,[r2,#0x10]
00032c  4382              BICS     r2,r2,r0
00032e  4b10              LDR      r3,|L1.880|
000330  611a              STR      r2,[r3,#0x10]
                  |L1.818|
;;;1228     }
;;;1229   }
000332  4770              BX       lr
;;;1230   
                          ENDP

                  RCC_BackupResetCmd PROC
;;;1236     */
;;;1237   void RCC_BackupResetCmd(FunctionalState NewState)
000334  4912              LDR      r1,|L1.896|
;;;1238   {
;;;1239     /* Check the parameters */
;;;1240     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1241     *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
000336  3940              SUBS     r1,r1,#0x40
000338  6008              STR      r0,[r1,#0]
;;;1242   }
00033a  4770              BX       lr
;;;1243   
                          ENDP

                  RCC_ClockSecuritySystemCmd PROC
;;;1249     */
;;;1250   void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
00033c  490f              LDR      r1,|L1.892|
;;;1251   {
;;;1252     /* Check the parameters */
;;;1253     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1254     *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
00033e  64c8              STR      r0,[r1,#0x4c]
;;;1255   }
000340  4770              BX       lr
;;;1256   
                          ENDP

                  RCC_MCOConfig PROC
;;;1281     */
;;;1282   void RCC_MCOConfig(uint8_t RCC_MCO)
000342  490b              LDR      r1,|L1.880|
;;;1283   {
;;;1284     /* Check the parameters */
;;;1285     assert_param(IS_RCC_MCO(RCC_MCO));
;;;1286   
;;;1287     /* Perform Byte access to MCO bits to select the MCO source */
;;;1288     *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO;
000344  71c8              STRB     r0,[r1,#7]
;;;1289   }
000346  4770              BX       lr
;;;1290   
                          ENDP

                  RCC_ClearFlag PROC
;;;1370     */
;;;1371   void RCC_ClearFlag(void)
000348  4809              LDR      r0,|L1.880|
;;;1372   {
;;;1373     /* Set RMVF bit to clear the reset flags */
;;;1374     RCC->CSR |= CSR_RMVF_Set;
00034a  6a40              LDR      r0,[r0,#0x24]
00034c  f0407080          ORR      r0,r0,#0x1000000
000350  4907              LDR      r1,|L1.880|
000352  6248              STR      r0,[r1,#0x24]
;;;1375   }
000354  4770              BX       lr
;;;1376   
                          ENDP

                  RCC_GetITStatus PROC
;;;1401     */
;;;1402   ITStatus RCC_GetITStatus(uint8_t RCC_IT)
000356  4601              MOV      r1,r0
;;;1403   {
;;;1404     ITStatus bitstatus = RESET;
000358  2000              MOVS     r0,#0
;;;1405     /* Check the parameters */
;;;1406     assert_param(IS_RCC_GET_IT(RCC_IT));
;;;1407   
;;;1408     /* Check the status of the specified RCC interrupt */
;;;1409     if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
00035a  4a05              LDR      r2,|L1.880|
00035c  6892              LDR      r2,[r2,#8]
00035e  420a              TST      r2,r1
000360  d001              BEQ      |L1.870|
;;;1410     {
;;;1411       bitstatus = SET;
000362  2001              MOVS     r0,#1
000364  e000              B        |L1.872|
                  |L1.870|
;;;1412     }
;;;1413     else
;;;1414     {
;;;1415       bitstatus = RESET;
000366  2000              MOVS     r0,#0
                  |L1.872|
;;;1416     }
;;;1417   
;;;1418     /* Return the RCC_IT status */
;;;1419     return  bitstatus;
;;;1420   }
000368  4770              BX       lr
;;;1421   
                          ENDP

                  RCC_ClearITPendingBit PROC
;;;1447     */
;;;1448   void RCC_ClearITPendingBit(uint8_t RCC_IT)
00036a  4901              LDR      r1,|L1.880|
;;;1449   {
;;;1450     /* Check the parameters */
;;;1451     assert_param(IS_RCC_CLEAR_IT(RCC_IT));
;;;1452   
;;;1453     /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
;;;1454        pending bits */
;;;1455     *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
00036c  7288              STRB     r0,[r1,#0xa]
;;;1456   }
00036e  4770              BX       lr
;;;1457   
                          ENDP

                  |L1.880|
                          DCD      0x40021000
                  |L1.884|
                          DCD      0xf8ff0000
                  |L1.888|
                          DCD      0xfef6ffff
                  |L1.892|
                          DCD      0x42420000
                  |L1.896|
                          DCD      0x42420480
                  |L1.900|
                          DCD      0x007a1200
                  |L1.904|
                          DCD      0x003d0900
                  |L1.908|
                          DCD      ||.data||

                          AREA ||.data||, DATA, ALIGN=0

                  APBAHBPrescTable
000000  00000000          DCB      0x00,0x00,0x00,0x00
000004  01020304          DCB      0x01,0x02,0x03,0x04
000008  01020304          DCB      0x01,0x02,0x03,0x04
00000c  06070809          DCB      0x06,0x07,0x08,0x09
                  ADCPrescTable
000010  02040608          DCB      0x02,0x04,0x06,0x08
