; generated by ARM C/C++ Compiler with , RVCT4.0 [Build 524] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\obj\misc.o --depend=.\obj\misc.d --device=DARMSTM --apcs=interwork -O0 -I.\FWlib\inc -I.\user -I.\CM3 -Id:\Keil\ARM\INC\ST\STM32F10x -D__MICROLIB -DUSE_STDPERIPH_DRIVER -DSTM32F10X_MD --omf_browse=.\obj\misc.crf FWlib\SRC\misc.c]
                          THUMB

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  NVIC_PriorityGroupConfig PROC
;;;95       */
;;;96     void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
000000  4932              LDR      r1,|L1.204|
;;;97     {
;;;98       /* Check the parameters */
;;;99       assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
;;;100      
;;;101      /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
;;;102      SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
000002  4301              ORRS     r1,r1,r0
000004  4a32              LDR      r2,|L1.208|
000006  6011              STR      r1,[r2,#0]
;;;103    }
000008  4770              BX       lr
;;;104    
                          ENDP

                  NVIC_Init PROC
;;;111      */
;;;112    void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
00000a  b570              PUSH     {r4-r6,lr}
;;;113    {
;;;114      uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
00000c  2100              MOVS     r1,#0
00000e  2300              MOVS     r3,#0
000010  220f              MOVS     r2,#0xf
;;;115      
;;;116      /* Check the parameters */
;;;117      assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
;;;118      assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));  
;;;119      assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
;;;120        
;;;121      if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
000012  78c4              LDRB     r4,[r0,#3]
000014  b30c              CBZ      r4,|L1.90|
;;;122      {
;;;123        /* Compute the Corresponding IRQ Priority --------------------------------*/    
;;;124        tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
000016  4c2e              LDR      r4,|L1.208|
000018  6824              LDR      r4,[r4,#0]
00001a  f40464e0          AND      r4,r4,#0x700
00001e  f5c464e0          RSB      r4,r4,#0x700
000022  0a21              LSRS     r1,r4,#8
;;;125        tmppre = (0x4 - tmppriority);
000024  f1c10304          RSB      r3,r1,#4
;;;126        tmpsub = tmpsub >> tmppriority;
000028  40ca              LSRS     r2,r2,r1
;;;127    
;;;128        tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
00002a  7844              LDRB     r4,[r0,#1]
00002c  fa04f103          LSL      r1,r4,r3
;;;129        tmppriority |=  NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
000030  7884              LDRB     r4,[r0,#2]
000032  4014              ANDS     r4,r4,r2
000034  4321              ORRS     r1,r1,r4
;;;130        tmppriority = tmppriority << 0x04;
000036  0109              LSLS     r1,r1,#4
;;;131            
;;;132        NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
000038  4c26              LDR      r4,|L1.212|
00003a  7806              LDRB     r6,[r0,#0]
00003c  55a1              STRB     r1,[r4,r6]
;;;133        
;;;134        /* Enable the Selected IRQ Channels --------------------------------------*/
;;;135        NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
00003e  7804              LDRB     r4,[r0,#0]
000040  f004051f          AND      r5,r4,#0x1f
000044  2401              MOVS     r4,#1
000046  40ac              LSLS     r4,r4,r5
000048  7805              LDRB     r5,[r0,#0]
00004a  116d              ASRS     r5,r5,#5
00004c  f04f26e0          MOV      r6,#0xe000e000
000050  eb060585          ADD      r5,r6,r5,LSL #2
000054  f8c54100          STR      r4,[r5,#0x100]
000058  e009              B        |L1.110|
                  |L1.90|
;;;136          (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
;;;137      }
;;;138      else
;;;139      {
;;;140        /* Disable the Selected IRQ Channels -------------------------------------*/
;;;141        NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
00005a  7804              LDRB     r4,[r0,#0]
00005c  f004041f          AND      r4,r4,#0x1f
000060  2501              MOVS     r5,#1
000062  40a5              LSLS     r5,r5,r4
000064  4c1c              LDR      r4,|L1.216|
000066  7806              LDRB     r6,[r0,#0]
000068  1176              ASRS     r6,r6,#5
00006a  f8445026          STR      r5,[r4,r6,LSL #2]
                  |L1.110|
;;;142          (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
;;;143      }
;;;144    }
00006e  bd70              POP      {r4-r6,pc}
;;;145    
                          ENDP

                  NVIC_SetVectorTable PROC
;;;155      */
;;;156    void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
000070  4a1a              LDR      r2,|L1.220|
;;;157    { 
;;;158      /* Check the parameters */
;;;159      assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
;;;160      assert_param(IS_NVIC_OFFSET(Offset));  
;;;161       
;;;162      SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
000072  400a              ANDS     r2,r2,r1
000074  4302              ORRS     r2,r2,r0
000076  4b16              LDR      r3,|L1.208|
000078  1f1b              SUBS     r3,r3,#4
00007a  601a              STR      r2,[r3,#0]
;;;163    }
00007c  4770              BX       lr
;;;164    
                          ENDP

                  NVIC_SystemLPConfig PROC
;;;174      */
;;;175    void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
00007e  b141              CBZ      r1,|L1.146|
;;;176    {
;;;177      /* Check the parameters */
;;;178      assert_param(IS_NVIC_LP(LowPowerMode));
;;;179      assert_param(IS_FUNCTIONAL_STATE(NewState));  
;;;180      
;;;181      if (NewState != DISABLE)
;;;182      {
;;;183        SCB->SCR |= LowPowerMode;
000080  4a13              LDR      r2,|L1.208|
000082  1d12              ADDS     r2,r2,#4
000084  6812              LDR      r2,[r2,#0]
000086  4302              ORRS     r2,r2,r0
000088  f04f23e0          MOV      r3,#0xe000e000
00008c  f8c32d10          STR      r2,[r3,#0xd10]
000090  e007              B        |L1.162|
                  |L1.146|
;;;184      }
;;;185      else
;;;186      {
;;;187        SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
000092  4a0f              LDR      r2,|L1.208|
000094  1d12              ADDS     r2,r2,#4
000096  6812              LDR      r2,[r2,#0]
000098  4382              BICS     r2,r2,r0
00009a  f04f23e0          MOV      r3,#0xe000e000
00009e  f8c32d10          STR      r2,[r3,#0xd10]
                  |L1.162|
;;;188      }
;;;189    }
0000a2  4770              BX       lr
;;;190    
                          ENDP

                  SysTick_CLKSourceConfig PROC
;;;198      */
;;;199    void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
0000a4  2804              CMP      r0,#4
;;;200    {
;;;201      /* Check the parameters */
;;;202      assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
;;;203      if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
0000a6  d108              BNE      |L1.186|
;;;204      {
;;;205        SysTick->CTRL |= SysTick_CLKSource_HCLK;
0000a8  f04f21e0          MOV      r1,#0xe000e000
0000ac  6909              LDR      r1,[r1,#0x10]
0000ae  f0410104          ORR      r1,r1,#4
0000b2  f04f22e0          MOV      r2,#0xe000e000
0000b6  6111              STR      r1,[r2,#0x10]
0000b8  e007              B        |L1.202|
                  |L1.186|
;;;206      }
;;;207      else
;;;208      {
;;;209        SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
0000ba  f04f21e0          MOV      r1,#0xe000e000
0000be  6909              LDR      r1,[r1,#0x10]
0000c0  f0210104          BIC      r1,r1,#4
0000c4  f04f22e0          MOV      r2,#0xe000e000
0000c8  6111              STR      r1,[r2,#0x10]
                  |L1.202|
;;;210      }
;;;211    }
0000ca  4770              BX       lr
;;;212    
                          ENDP

                  |L1.204|
                          DCD      0x05fa0000
                  |L1.208|
                          DCD      0xe000ed0c
                  |L1.212|
                          DCD      0xe000e400
                  |L1.216|
                          DCD      0xe000e180
                  |L1.220|
                          DCD      0x1fffff80
